What Are Programmable Logic Devices?

Programmable logic devices (PLDs) are integrated circuits that implement digital logic functions determined by the user through a configuration process after manufacture, rather than by a fixed design baked in at the foundry. By allowing engineers to load custom logic into an off-the-shelf component, PLDs eliminate the tooling cost and lead time of application-specific integrated circuits (ASICs) for many applications. The category spans a wide range, from small simple PLDs (SPLDs) capable of replacing a handful of TTL gate packages, through complex programmable logic devices (CPLDs) suited to control logic, up to field-programmable gate arrays (FPGAs) that rival the capacity of small ASICs.

The concept originated in the 1970s with fuse-programmable read-only memory used as a lookup table and with programmable array logic (PAL) devices. Monolithic Memories introduced the PAL in 1978, and it quickly displaced many discrete gate arrays in digital systems. Subsequent decades brought erasable and reprogrammable variants, then the FPGA architecture introduced by Xilinx in 1985, which scaled to logic capacities orders of magnitude beyond earlier PLDs.

Types of Programmable Logic Devices

SPLDs encompass programmable logic arrays (PLAs), PALs, and generic array logic (GAL) devices. PLAs provide two programmable planes: an AND plane generating product terms and an OR plane combining them, allowing flexible sum-of-products implementations. PALs fix the OR plane and program only the AND plane, trading some flexibility for lower propagation delay. GALs added EEPROM reprogrammability to the PAL architecture in the 1980s, allowing devices to be erased and reloaded in the field. CPLDs extend the SPLD concept with multiple interconnected macrocell blocks and a global routing matrix, retaining the deterministic timing and non-volatile configuration that makes them suited for power-sensitive and boot-critical applications. FPGAs organize logic into arrays of look-up-table-based configurable logic blocks (CLBs) with a programmable routing fabric, providing much higher capacity and the ability to implement complex pipelined datapath designs. The IEEE Design and Test tutorial on FPGA and CPLD Architectures gives a detailed account of how these device families are organized and how their architectural differences affect design decisions.

High-Level Synthesis and Design Flow

Designing logic for PLDs traditionally required writing register-transfer level (RTL) descriptions in a hardware description language (HDL) such as VHDL or Verilog, both of which are defined by IEEE standards (IEEE 1076 and IEEE 1364 respectively). High-level synthesis (HLS) tools have extended this flow upward, allowing designers to write algorithms in C, C++, or SystemC and have the tools automatically generate RTL. HLS is particularly valuable for signal processing and machine learning inference applications, where a mathematical description of an algorithm can be translated directly into pipelined hardware without manual RTL coding. Once RTL is available, synthesis, placement, routing, and timing analysis tools complete the implementation and generate the bitstream or configuration data that programs the device. Cadence's FPGA design resource on CPLD vs. FPGA selection outlines how designers choose between device families based on complexity, timing, and power requirements.

Configuration and Reprogrammability

PLDs differ in how they store their configuration. Fuse-based SPLDs are programmed once and cannot be changed. EEPROM-based CPLDs retain configuration through power cycles and can be reprogrammed in the system using JTAG boundary-scan interfaces defined in IEEE Standard 1149.1. SRAM-based FPGAs lose their configuration at power-down and must be reloaded from external flash memory or a host processor at startup, but this architecture allows unlimited reprogramming cycles and dynamic partial reconfiguration during operation.

Applications

Programmable logic devices have applications in a wide range of fields, including:

• Telecommunications infrastructure for protocol conversion and data framing
• Defense electronics for radar front-end processing and signal classification
• Industrial control systems requiring deterministic timing and harsh-environment reliability
• Medical imaging equipment for data acquisition and real-time reconstruction
• Consumer electronics for USB and video interface bridging
• Academic and research prototyping of custom processor architectures