What Is High Level Synthesis?

High level synthesis (HLS) is a design automation process that translates an algorithmic or behavioral description of a digital system into a register-transfer level (RTL) implementation suitable for ASIC or FPGA fabrication. Rather than specifying the exact cycle-by-cycle behavior of hardware, a designer describes what the circuit must compute, and the HLS tool determines how to implement that computation in logic. The technique emerged from research in the 1980s as a response to the growing complexity of digital systems and the limitations of manual RTL design, and it has since become a central component of modern electronic design automation (EDA) workflows.

HLS draws on compiler theory, scheduling algorithms, and hardware architecture principles. Its inputs are typically written in C, C++, or SystemC, and its outputs are synthesizable Verilog or VHDL descriptions that downstream tools can place and route onto physical silicon or programmable devices. The approach bridges the gap between software-oriented algorithmic thinking and the hardware constraints of timing, area, and power.

The Synthesis Process

The core task of HLS is mapping a behavioral description onto hardware resources. This involves three interrelated steps: scheduling, allocation, and binding. Scheduling assigns each operation in the description to a specific clock cycle, respecting data dependencies and timing constraints. Allocation determines how many hardware units of each type (adders, multipliers, registers, memory ports) the design will use. Binding then maps each operation to a specific hardware unit, and each variable to a specific register or memory element. As described in introductory treatments of the field published in IEEE Design and Test, these three steps are tightly coupled and must be solved together to produce efficient results. Changes to the scheduling affect what sharing of hardware units is possible, which in turn affects area and timing.

Input Languages and Design Constraints

Modern HLS tools accept C and C++ with hardware-oriented pragmas or directives that guide the synthesis engine. These directives control loop unrolling, pipelining, memory partitioning, and interface protocols without changing the functional semantics of the code. The AMD Vitis HLS tool, one of the most widely used commercial implementations, generates RTL from C/C++ functions and integrates with the Vivado design suite for subsequent place-and-route. SystemC, a C++ library that adds hardware modeling constructs, is also commonly used when the input description needs to express more structural detail. MathWorks HDL Coder provides a parallel path through MATLAB and Simulink for signal processing and control algorithm designers who prefer a dataflow-oriented entry point.

Quality of Results and Optimization

A persistent challenge in HLS is the quality-of-results (QoR) gap between human-crafted RTL and automatically generated RTL. Early HLS tools often produced circuits that were 2 to 3 times larger or slower than hand-written equivalents for the same algorithm. Research into improved scheduling heuristics, loop transformation, and dataflow analysis has narrowed this gap considerably. Work surveyed in IEEE conference publications on system-level and high-level synthesis shows that modern tools can approach hand-coded RTL quality for regular, compute-intensive kernels such as digital filters, matrix operations, and protocol state machines, while still lagging on irregular control-heavy designs. Designers often iterate between C-level simulation and synthesis, adjusting directives to meet area and timing budgets.

Applications

High level synthesis has applications across a range of domains, including:

• FPGA accelerator development for signal processing and machine learning inference
• ASIC prototyping and design-space exploration at the algorithmic level
• Programmable logic device programming for embedded control systems
• Rapid hardware implementation of cryptographic and compression algorithms
• Automotive and aerospace compute cores where functional correctness must be verified at the source level