What Are Programmable Logic Arrays?

Programmable logic arrays (PLAs) are a category of programmable logic device used to implement combinational digital logic in sum-of-products form without requiring custom mask fabrication. A PLA consists of two cascaded programmable gate planes: an AND plane that generates product terms from input variables and their complements, and an OR plane that combines selected product terms to form each output function. Both planes are configurable, giving the PLA more flexibility than simpler programmable devices such as programmable read-only memory (PROM). PLAs belong to the broader family of programmable logic devices (PLDs), which also includes programmable array logic (PAL) and, at larger scale, complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs).

PLAs emerged in the 1970s as a way to consolidate the combinational logic that would otherwise require many individual discrete gates or ROM lookup tables. Their ability to share product terms across multiple output functions made them area-efficient for implementing the control logic found in microprocessors, address decoders, and instruction decoders.

AND-OR Architecture

The defining structural feature of a PLA is its two-level AND-OR topology. Each input is presented in true and complemented form to a set of AND gates whose connections to the input lines can be programmed by blowing fusible links or configuring antifuse or EEPROM cells. The AND gate outputs, called product terms or implicants, are then routed to a second programmable array of OR gates, which combine selected product terms to produce each output. This arrangement allows the device to realize any sum-of-products Boolean expression within the capacity limits of the array. ScienceDirect's overview of programmable logic array design notes that both mask-programmable and field-programmable variants exist, with field-programmable parts allowing engineers to configure devices in the laboratory rather than at the foundry.

PLA vs. PAL

Programmable array logic (PAL) devices share the AND-plane-before-OR-plane topology but differ from PLAs in that only the AND plane is programmable; the OR plane is fixed, with each OR gate connected to a predetermined subset of AND gate outputs. This architectural simplification removes the delay associated with a second programmable routing stage, producing faster and more predictable timing at the cost of some flexibility in how product terms can be shared. The IEEE Design and Test tutorial on FPGA and CPLD Architectures places PLAs and PALs in context as the early representatives of programmable logic that later evolved into CPLDs and FPGAs. Generic array logic (GAL) devices, introduced by Lattice Semiconductor in the 1980s, added EEPROM-based reprogrammability to the PAL architecture, allowing devices to be erased and reconfigured in the field.

Logic Minimization and Implementation

Before loading a PLA, designers use Boolean minimization tools to reduce logic expressions to a minimal set of product terms, since the AND plane has a finite number of rows. The Quine-McCluskey algorithm and Karnaugh maps are classical methods for this reduction, and CAD tools such as the ESPRESSO logic minimizer automate the process for functions with many variables. Minimization is more critical for PLAs than for PLDs with fixed OR planes, because shared product terms benefit both output functions simultaneously. The VLSI Design resource on programmable logic array structures describes how this sharing property makes PLAs particularly efficient for multiple-output logic functions found in microprocessor control units.

Applications

Programmable logic arrays have applications in a wide range of fields, including:

• Microprocessor control unit implementation, including instruction decode and sequencing logic
• Address decoding in memory subsystems and bus interfaces
• State machine implementation in embedded controllers and communication devices
• Arithmetic logic units and format conversion circuits in digital systems
• Rapid prototyping of combinational logic before committing to ASIC fabrication