What Are Transmission Gates?

Transmission gates are bidirectional CMOS switching elements that pass or block a signal based on a control voltage. A standard transmission gate consists of an NMOS transistor and a PMOS transistor connected in parallel between an input and an output node, with complementary control signals applied to the respective gates. When the control signal is high, both transistors conduct, and the gate presents a low-resistance path for signals of any voltage level within the supply range. When the control signal is low, both transistors are off, and the gate presents a very high impedance. The complementary pairing solves the threshold voltage drop problem that occurs when a single NMOS or PMOS transistor is used alone as a switch.

Transmission gates are fundamental building blocks in digital VLSI design and analog sampling circuits. They appear in standard-cell libraries for field-programmable gate arrays, data converters, and custom integrated circuits, often offering significant transistor-count advantages over equivalent static CMOS implementations.

CMOS Implementation and Operation

The bidirectional symmetry of a transmission gate follows from the symmetrical nature of MOSFET operation. An NMOS transistor passes a logic-low signal cleanly but degrades a logic-high by a threshold voltage V_tn, which would corrupt digital logic levels. The PMOS transistor does the inverse: it passes a logic-high cleanly but degrades a logic-low. By placing both in parallel with complementary gate signals, the composite structure passes full-swing signals in either direction. The on-resistance of the combined device is the parallel combination of the two channel resistances, which varies with input voltage but remains substantially lower than either transistor alone. Cornell's VLSI design course materials on pass transistors and transmission gates describe the detailed V-I characteristics of this composite switch.

Pass Transistor Logic and Transistor Efficiency

In pass transistor logic (PTL), a design style that uses transmission gates as the primary switching element rather than standard inverting gates, complex Boolean functions can be realized with substantially fewer transistors than static CMOS. A two-to-one multiplexer built with transmission gates requires 6 transistors, compared to 14 in a fully static complementary CMOS implementation using NAND and NOR gates. An XOR gate using transmission gates requires approximately 8 transistors, versus 12 in static CMOS. These savings become significant in arithmetic-intensive circuits such as full adders, comparators, and carry-generate chains in arithmetic logic units. The University of Texas VLSI design lecture notes detail the transistor-count trade-offs between static CMOS and pass transistor logic in representative gate implementations.

Timing and Signal Integrity

The RC delay through a chain of transmission gates accumulates because the output of one gate drives the input resistance of the next. Unlike static CMOS, transmission gate outputs are not buffered, so charge sharing between node capacitances can degrade signal levels over long chains. Designers typically insert inverter buffers every four to six gates to restore full-swing logic levels and reduce cumulative delay. Charge injection, in which the charge stored in the gate oxide redistributes onto the output when the control signal switches, introduces an offset error in analog switching applications. Minimizing charge injection is a central concern in sample-and-hold circuits and switched-capacitor filters, where transmission gates serve as sampling switches. The ScienceDirect overview of transmission gate applications covers these timing and charge-related constraints in detail.

Applications

Transmission gates have applications in a range of fields, including:

• Digital logic, as multiplexers, XOR gates, and full adder cells in standard-cell and custom VLSI libraries
• Memory design, as access switches in static and dynamic RAM bit cells
• Analog sampling circuits, as switches in sample-and-hold stages and switched-capacitor filters
• Clock distribution, as gating elements for low-skew clock enable circuits
• Programmable logic, as configuration pass gates in FPGA routing architectures