What Are Application Specific Integrated Circuits?

Application specific integrated circuits (ASICs) are integrated circuit chips designed and fabricated to perform a defined set of functions for a particular application, rather than serving as general-purpose computing components. Unlike field-programmable gate arrays (FPGAs), which can be reconfigured after manufacture, or microprocessors, which execute arbitrary software, ASICs implement a fixed function in silicon. This specialization allows them to achieve higher performance, lower power consumption, and smaller physical area per computation than programmable alternatives, at the cost of substantial non-recurring engineering (NRE) investment during design and fabrication.

The ASIC design process involves hardware description language coding, logic synthesis, physical layout, and tape-out to a semiconductor foundry, followed by fabrication and post-silicon verification. Design cycles typically span several months and fabrication costs can range from hundreds of thousands to several million dollars, making ASICs economically viable only when production volumes are large enough to amortize those costs.

CMOS Logic Circuits and Digital ASIC Design

Most digital ASICs are implemented in complementary metal-oxide-semiconductor (CMOS) technology, which provides the combination of low static power dissipation and high noise margins required for dense, high-speed logic circuits. Standard cell design, one of the dominant ASIC methodologies, builds circuits from a library of pre-characterized logic cells, including inverters, flip-flops, multiplexers, and arithmetic units, that are automatically placed and routed by electronic design automation (EDA) tools. Gate array and full-custom design styles offer different tradeoffs between design effort and silicon efficiency. Technology scaling following Moore's Law has allowed ASIC designers to integrate billions of transistors on a single die, enabling complete systems on chip (SoCs) that combine processor cores, memory blocks, and dedicated accelerators. The IEEE Xplore library contains extensive literature on algorithm-hardware co-design methods for digital and mixed-signal integrated circuits, which is a central concern in modern ASIC development.

Analog Processing Circuits

Analog ASICs implement continuous-signal processing functions in silicon, including amplification, filtering, analog-to-digital conversion, phase-locked loops, and radio-frequency front ends. Unlike digital circuits, which operate on binary values, analog circuits must preserve signal fidelity across a continuous range and are sensitive to manufacturing variation, temperature, and noise. Mixed-signal ASICs combine analog and digital blocks on the same die, a combination common in sensor interfaces, power management units, and communication transceivers. CMOS technology supports both analog and digital circuits, though the aggressive scaling that benefits digital logic can degrade analog performance by reducing supply voltages and increasing device variability. Field-programmable analog arrays (FPAAs) offer a reconfigurable alternative to fixed analog ASICs for prototyping and low-volume applications, occupying a role analogous to FPGAs in the digital domain. The Springer chapter on Application Specific Integrated Circuits in the VLSI handbook provides a detailed overview of the mixed-signal design methodologies that bridge analog and digital subdisciplines within ASIC development.

AI Accelerators

A significant share of recent ASIC design activity has focused on hardware accelerators for machine learning inference and training. These AI accelerators, implemented as ASICs, provide far greater energy efficiency for matrix multiplication and convolution operations than general-purpose CPUs or GPUs by hardwiring the dataflow patterns that dominate neural network computation. Companies including Google (with its Tensor Processing Unit), Apple (with its Neural Engine), and several semiconductor startups have introduced inference ASICs for data centers and edge devices. The economic model of AI accelerator ASICs follows the same logic as other high-volume ASICs: the NRE cost is justified by the volume of chips deployed and the performance-per-watt advantage over programmable processors. Research documented in the ACM Digital Library's proceedings on compilers and synthesis for embedded systems explores the automatic generation of application-specific processors and accelerator datapaths, a methodology foundational to modern AI ASIC design.

Applications

Application specific integrated circuits are used across a wide range of industries and systems, including:

• Consumer electronics, including smartphones, tablets, and wearable devices
• Data center AI inference engines and high-performance computing accelerators
• Telecommunications base stations and network switching equipment
• Automotive systems for advanced driver assistance and in-vehicle networking
• Medical devices such as implantable sensors and portable diagnostic equipment
• Cryptocurrency mining hardware optimized for proof-of-work hash functions