Conferences related to Semiconductor device testing

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2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)

Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE Applied Power Electronics Conference and Exposition (APEC)

APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics


2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.


IECON 2020 - 46th Annual Conference of the IEEE Industrial Electronics Society

IECON is focusing on industrial and manufacturing theory and applications of electronics, controls, communications, instrumentation and computational intelligence.


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Periodicals related to Semiconductor device testing

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Design & Test of Computers, IEEE

IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of ...


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Most published Xplore authors for Semiconductor device testing

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Xplore Articles related to Semiconductor device testing

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IEE Colloquium on 'Thermal Management in Power Electronics Systems' (Digest No.065)

IEE Colloquium on Thermal Management in Power Electronics Systems, 1993

None


IEE Colloquium on 'Measurements and Modelling of Microwave Devices and Circuits' (Digest no.124)

IEE Colloquium on Measurements and Modelling of Microwave Devices and Circuits, 1989

None


Practical application of a wafer level reliability qualification

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS), 1994

Deficiencies in the traditional approach to ensuring product reliability (e.g. package level testing) were first noted way back in the early 1970's. However, it was not until the late 1980's to early 1990's that WLRC was seriously considered and began to be implemented across the industry. This new approach for achieving greater levels of reliability required a fundamental change from ...


"Static Or Dynamic", The Selection Process For A Memory System

COMPCON '77, 1977

None


On comparing functional fault coverage and defect coverage for memory testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999

The manufacturing of high-quality and reliable semiconductor memories is very important. Many memory testing algorithms have been proposed to improve the quality of semiconductor memories by screening out different memory functional faults. However, the relationships between memory function fault types and the types of defects which cause the functional faults are not well understood. Therefore, the effectiveness of memory testing ...


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Educational Resources on Semiconductor device testing

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IEEE-USA E-Books

  • IEE Colloquium on 'Thermal Management in Power Electronics Systems' (Digest No.065)

    None

  • IEE Colloquium on 'Measurements and Modelling of Microwave Devices and Circuits' (Digest no.124)

    None

  • Practical application of a wafer level reliability qualification

    Deficiencies in the traditional approach to ensuring product reliability (e.g. package level testing) were first noted way back in the early 1970's. However, it was not until the late 1980's to early 1990's that WLRC was seriously considered and began to be implemented across the industry. This new approach for achieving greater levels of reliability required a fundamental change from the mind set of reliability verification on finished products (screening the outputs) to comprehending and controlling the various factors that determine reliability (controlling the inputs). This mind set is known as "building-in" or "designing-in" reliability and envisions a total reliability assurance and improvement strategy that is executed at all stages of semiconductor manufacturing. To meet the challenge of continuous improvement, it is now a corporate policy that a WLRC program be required at all R&D and production facilities with the intention of determining and eliminating all faults at their source of origin. Emphasis is placed on the use of wafer level reliability testing for introducing and qualifying new semiconductor technology and controlling production once technology has been transferred to the wafer fab. The description, philosophy and issues of integrating the WLRC program into a manufacturing environment have been described previously. Here a practical application is presented. As an example, the development, execution and results of a WLR qualification and production control plan for an advanced, submicron, triple-level metal CMOS process is provided.

  • "Static Or Dynamic", The Selection Process For A Memory System

    None

  • On comparing functional fault coverage and defect coverage for memory testing

    The manufacturing of high-quality and reliable semiconductor memories is very important. Many memory testing algorithms have been proposed to improve the quality of semiconductor memories by screening out different memory functional faults. However, the relationships between memory function fault types and the types of defects which cause the functional faults are not well understood. Therefore, the effectiveness of memory testing algorithms based on the functional fault models cannot be realistically determined. This paper evaluates the effectiveness of the memory testing algorithms based on the defect coverage by comparing the defect coverage of known memory testing algorithms and the functional fault coverage of the same testing algorithms using the same defect statistics. The experimental results show that the differences among the defect coverage of the 11 memory testing algorithms other than checkerboard and sliding diagonal tests were not significant as previously believed using memory functional fault coverage as the coverage metric.

  • Failure Reporting, Analysis And Corrective Action System In The US Semiconductor Manufacturing Equipment Industry: A Continuous Improvement Process

    None

  • VIA/BGA/sup (R)/: a low-cost, high-performance packaging technology for broadband telecommunications

    A ceramic BGA packaging technology for broadband applications such as LMDS and SONET/SDH is described. The package is designed for the bandwidth of DC-32 GHz. Manufactured on VIA/PLANE/sup (R)/ using semiconductor processing techniques in an array format, it provides the ability to assemble and test the devices in arrays for maximum productivity. The paper describes the electromagnetic modeling, design, manufacture and testing of the package. Its electrical performance is compared with the theoretical model. The thermal model of the package with device on PCB is also presented. The package attributes are compared with the conventional leaded, microstrip/stripline and leadless formats.

  • Semiconductor perspective on test standards

    Developing testable products cost-effectively requires that a standard, such as JTAG and the IEEE P-1149, be adopted. The system developer and semiconductor manufacturer need to share in this development effort to accelerate adoption. The system developer must gain a better understanding of the total cost of ownership for a testable vs. a nontestable product and the semiconductor manufacturer must be willing to provide initial product offerings before a well defined and quantified market exists. Efforts must be put in place to implement standards in software tools and data formats required to support test.<<ETX>>

  • Studies on the Possibilities of In-Line Die Attach Characterization of Semiconductor Devices

    The qualification of the die attach of semiconductor devices is a very important element of predicting the reliability of the package, as the temperature of the chip is strongly affected by the quality of the die attach. This paper describes our latest findings on die attach quality testing of semiconductor devices using short term thermal transient measurements. Using estimates from simulations as well as from measured structure functions of power transistors with known die attach quality we found that cca the first 100ms section of thermal transients is sufficient to draw conclusion on die attach quality. In case of in-line application of the short term thermal transient measurements however, there are different difficulties such as lack of time for K-factor calibration of the individual devices under test. In this paper we describe certain techniques which have been validated on large number of power LEDs with the aim of application in in line testing of die attach quality.

  • Finite element simulation of the temperature cycling tests

    Temperature cycling tests are commonly used in the semiconductor industry to determine the number of cycles to failure and to predict reliability of the solder joints in the surface mount technology packages. In this paper, the thermomechanical fatigue of Pb40/Sn60 solder joint in a leadless ceramic chip carrier package is studied and temperature cycling test is simulated by using a finite element procedure with the disturbed state concept (DSC) constitutive models. The progress of disturbance (damage) and the energy dissipated in the solder joint during thermal cycling are predicted. It is shown that the disturbance criterion used follows a similar path as the energy dissipation in the system. Moreover, the comparisons between the test data and the finite element analysis show that a finite element procedure using the DSC material models can be instrumental in reliability analysis and to predict the number of cycles to failure of a solder joint. Furthermore, the analysis gives a good picture of the progress of the failure mechanism and the disturbance in the solder joint.



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