Semiconductor device breakdown
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2021 IEEE Photovoltaic Specialists Conference (PVSC)
Photovoltaic materials, devices, systems and related science and technology
Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies
the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
The conference will provide a forum for discussions and presentations of advancements inknowledge, new methods and technologies relevant to industrial electronics, along with their applications and future developments.
Meeting of academia and research professionals to discuss reliability challenges.
Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Electrical insulation common to the design and construction of components and equipment for use in electric and electronic circuits and distribution systems at all frequencies.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Proceedings of International Symposium on Semiconductor Manufacturing, 1995
Tries to evaluate the investment effect ofthe whole factory by grasping the process cost precisely, classifying its structure, and identifying useless cost factors. As an evaluation index, we defined and used the CPO (Cost of Process Ownership), which is the cost per wafer in each process step based on the configuration of equipment installed in the factory and the configuration ...
IEEE Transactions on Power Electronics, 2000
This paper analyzes an anomalous failure mechanism detected on last generation low voltage power metal oxide semiconductor (MOS) devices at low drain current. Such a behavior, apparently due to a kind of second breakdown phenomenon, has been scarcely considered in literature, as well as in manufacturer data sheets, although extensive experimental tests show that it is a common feature of ...
1999 57th Annual Device Research Conference Digest (Cat. No.99TH8393), 1999
Owing to high critical electrical breakdown field and large energy gap, SiC has been established as the most promising candidate for high-voltage power semiconductor devices. In the past few years, several high-voltage vertical MOS devices have been demonstrated in SiC, whereas only a 2.6 KV lateral SiC MOSFET has been reported so far. Lateral integrable REduced SURface Field (RESURF) devices ...
IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings, 1996
Conventional intuition of semiconductor wafer fab performance relies on assumptions of linear work flow and fixed (deterministic) behavior of the fab equipment's breakdown and capacity. This intuition is used to analyze fab capacity by using simple mathematical models in a "spreadsheet" fashion to obtain feasibility bounds on capacity (wafers out/unit time), cycle time (or lead time) and work-in-progress levels. However, ...
2006 IEEE International Integrated Reliability Workshop Final Report, 2006
In this paper a new technique for predicting gate oxide reliability with high confidence from easily accessible ramped voltage stress data is proposed. Given the parameter of the RVT stress profile, the concept of equivalence is successfully applied to convert stress time data at each ramp stress level to corresponding accumulated equivalent ages at any one stress level. Taking into ...
Semiconductor Laser Development at Hisense Photonics - Yanfeng Lao - IPC 2018
Honors 2020: Chenming Hu Wins the IEEE Medal of Honor
Overview of SDRJ - Yoshihiro Hayashi at INC 2019
2015 IEEE Honors: IEEE Jun-ichi Nishizawa Medal - Dimitri A. Antoniadis
GaN HEMTs and Schottky Diodes
The Era of AI Hardware - 2018 IEEE Industry Summit on the Future of Computing
Micrel Ripple Blocker
ASC-2014 SQUIDs 50th Anniversary: 2 of 6 - John Clarke - The Ubiquitous SQUID
2011 Medal of Honor - Morris Chang
IMS 2011 Microapps - Beyond the S-Parameter: The Benefits of Nonlinear Device Models
APEC 2012 - Dan Kinzer Plenary
Semiconductor Nanowires for Optoeletronics Applications: An IPC Keynote with Chennupati Jagadish
LPIRC: On Device Vision, Google AI-Style
The Future of Semiconductor: Moore's Law Plus - IEEE Rebooting Computing Industry Summit 2017
Infineon: Innovative Semiconductor Solutions
IMS 2011 Microapps - Advanced Terahertz Device Characterization
IMS 2014: Broadband Continuous-mode Power Amplifiers
IMS 2011 Microapps - Improved Microwave Device Characterization and Qualification Using Affordable Microwave Microprobing Techniques for High-Yield Production of Microwave Components
Tries to evaluate the investment effect ofthe whole factory by grasping the process cost precisely, classifying its structure, and identifying useless cost factors. As an evaluation index, we defined and used the CPO (Cost of Process Ownership), which is the cost per wafer in each process step based on the configuration of equipment installed in the factory and the configuration of product types manufactured there. This index was developed by making some improvements to the CEO (Cost of Equipment Ownership) model. We will report the definition ofthe CPO we are using and some examples of CPO utilization.
This paper analyzes an anomalous failure mechanism detected on last generation low voltage power metal oxide semiconductor (MOS) devices at low drain current. Such a behavior, apparently due to a kind of second breakdown phenomenon, has been scarcely considered in literature, as well as in manufacturer data sheets, although extensive experimental tests show that it is a common feature of modern low voltage metal oxide semiconductor held effect transistor (MOSFET) devices. The paper starts by analyzing some failures, systematically observed on low voltage power MOSFET devices, inside the theoretical forward biased safe operating area. Such failures are then related to an unexpected thermal instability of the considered devices. Experimental tests have shown that in the considered devices the temperature coefficient is positive for a very wide drain current range, also including the maximum value. Such a feature causes hot spot phenomena in the devices, as confirmed by microscope inspection of the failed devices. Finally, it is theoretically demonstrated that the thermal instability is a side effect of the progressive die size and process scaling down. As a result, latest power MOSFETs, albeit more efficient and compact, are less robust than older devices at low drain currents, thus requiring specific circuit design techniques.
Owing to high critical electrical breakdown field and large energy gap, SiC has been established as the most promising candidate for high-voltage power semiconductor devices. In the past few years, several high-voltage vertical MOS devices have been demonstrated in SiC, whereas only a 2.6 KV lateral SiC MOSFET has been reported so far. Lateral integrable REduced SURface Field (RESURF) devices are key building blocks for high-voltage power ICs. In this work, we present the first experimental demonstration of a n-channel lateral RESURF MOSFET fabricated on 4H-SiC. The devices exhibit a blocking voltage in excess of 1200 V with a best specific on-resistance of 4 ohm-cm/sup 2/.
Conventional intuition of semiconductor wafer fab performance relies on assumptions of linear work flow and fixed (deterministic) behavior of the fab equipment's breakdown and capacity. This intuition is used to analyze fab capacity by using simple mathematical models in a "spreadsheet" fashion to obtain feasibility bounds on capacity (wafers out/unit time), cycle time (or lead time) and work-in-progress levels. However, assumptions of linearity and fixed behavior are not always valid, especially when strategic analysis needs to be done over long time horizons. This paper demonstrates the effects of such non-linearities and random (stochastic) behavior. This is done by modeling simple fab scenarios using advanced mathematical and discrete-event simulation tools. In particular, effects of a high degree of variance on equipment availability are investigated using serial representations of a manufacturing line. The impact of setup change-over times is also analyzed through random queuing scenarios in order to arrive at more accurate results of the line loading phenomenon. These results are then statistically analyzed to provide a contrast to conventional intuition.
In this paper a new technique for predicting gate oxide reliability with high confidence from easily accessible ramped voltage stress data is proposed. Given the parameter of the RVT stress profile, the concept of equivalence is successfully applied to convert stress time data at each ramp stress level to corresponding accumulated equivalent ages at any one stress level. Taking into account these ages until breakdown, failure probabilities with the parameters of the stress-life relationship being the only fitting parameters can directly be computed and converted to TDDB failure distributions
We present a novel physical random number generator (RNG) that uses a metal- oxide semiconductor (MOS) capacitor after soft breakdown (SBD) as a random source. It is known that the electrical properties of MOS capacitors after SBD show large fluctuation. When the resistor in an astable multivibrator is replaced with an MOS capacitor after SBD, the multivibrator converts the noise signal into a rectangular wave whose period fluctuates randomly. A 1-bit counter and a flip-flop are used to generate random numbers from the fluctuating rectangular wave. Some high-level tests indicate that the generated random numbers have excellent quality for cryptographic applications. Even though our circuit is small and can be constructed using about 20 complementary-MOS logic gates and several passive devices, high- quality random numbers such as those generated by large physical RNGs can be obtained.
As a rule, very high power converters are custom designed. One of the most important problems is a phenomenon of high current flow during internal short circuits caused by semiconductor device breakdown. This situation may result in device package explosion and other damage caused by the destructive action of electrodynamic forces. The proposal of fast fuses elimination, commonly used as short-circuit protection, requires the determination of device explosion strength characteristics (peak value of case destroying current vs. time). Then it is necessary to design such a level of the converter load that the device current will not exceed the admissible value before the tripping of the AC supply circuit-breaker. In the paper, overcurrent protection methods are analysed. Some experiences and test results in this field are given. The mechanisms of destruction of power semiconductor devices caused by very high short-circuit currents are discussed. In conclusion, guidelines for the design of power electronic equipment without fast semiconductor fuse overcurrent protection are given.
Currently, the occurrence of microplasma regions in PN junctions is attributed to crystal lattice imperfections. As a rule, these regions feature lower strong-field avalanche ionization breakdown voltages than other homogeneous junction regions. The existence of such regions may lead to local avalanche breakdowns occurring in reverse-biased PN junctions at certain voltages. Macroscopically, these breakdowns are manifested as microplasma noise. Studying the current conductivity bi-stable mechanism thus may be used as an efficient tool to evaluate the PN junction inhomogeneity.
Some of the important characteristics of the semiconductor wafer fabrication factories are re-entrant process flows, a dynamic and uncertain environment, resource sharing, unpredicted machine breakdown, etc. So, the design, implementation, and operation of manufacturing systems is a complex task. Without powerful modeling techniques it is practically impossible to efficiently design a manufacturing system. Modeling the system is a premise work to optimize the properties of the system. In this paper, a modeling approach based on queueing generalized stochastic colored timed Petri-net (QGSCTPN) for semiconductor wafer fabrication is presented. The main idea of this tool is to combine colored timed Petri nets with the queuing systems, and it aims to make simulation over the model more efficient. It also can be used to model various detail of manufacturing system such as re-entrant processing, machine failures, loading and unloading, etc., pertaining to wafer fabrication. Using the industrial example as a case study, this paper aims at presenting some theoretical methods and their application using a modeling tool during the design of manufacturing systems. Finally, the aim of next-step work is put-forward.
The efficiency of a new junction termination structure for improvement of breakdown properties of semiconductor radiation detectors is investigated. The structure consists of a diffused resistor winding around the active junction in a spiral fashion. The current flow through the spiral enables controlled potential distribution along the spiral turns and thus controlled depletion spreading from the main junction, efficiently preventing premature avalanche breakdown. Both multiple guard-ring structures and spiral structures have good termination shown properties typically three to five times higher than breakdown voltages of diodes without junction termination. The breakdown voltages of spiral junction termination structures are only weakly influenced by changes in substrate doping concentration caused by neutron irradiation. They can thus be considered for termination of future semiconductor radiation detectors.
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