Conferences related to Microprocessor chips

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2020 IEEE Frontiers in Education Conference (FIE)

The Frontiers in Education (FIE) Conference is a major international conference focusing on educational innovations and research in engineering and computing education. FIE 2019 continues a long tradition of disseminating results in engineering and computing education. It is an ideal forum for sharing ideas, learning about developments and interacting with colleagues inthese fields.


2020 IEEE Applied Power Electronics Conference and Exposition (APEC)

APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)

Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies



Periodicals related to Microprocessor chips

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Antennas and Wireless Propagation Letters, IEEE

IEEE Antennas and Wireless Propagation Letters (AWP Letters) will be devoted to the rapid electronic publication of short manuscripts in the technical areas of Antennas and Wireless Propagation.


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems Magazine, IEEE



Most published Xplore authors for Microprocessor chips

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Xplore Articles related to Microprocessor chips

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Microprocessor design for inteligent point-of-sale terminals

Computer, 1974

A point-of-sale (POS) terminal, besides serving as an ordinary isolated cash register, is also part of a retail data collection system. The system emphasis is on data collection, although minimal computational capability is also required. The rate of data input to this system is largely limited by the speed of the operator. These aspects influence terminal design. This article describes ...


Why should we do 3D integration?

2008 45th ACM/IEEE Design Automation Conference, 2008

3D integration offers a technology that meets the requirements of the current trend in high performance microprocessors. It offers the opportunity to continue the performance trends the industry enjoyed in the past. To take advantage of this opportunity system architecture and design needs to utilize the new possibilities that 3D integration provides.


CMOS design of cellular APAPs and FPAPAPs: an overview

Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications, 2002

CNN-based analog visual microprocessors have similarities with the so-called Single Instruction Multiple Data systems, although they work directly on analog signal representations obtained through embedded optical sensors and hence do not need a frontend sensory plane or analog-to-digital converters. The architecture of these visual microprocessors is illustrated in the paper through two prototype chips, namely: ACE4K and ACE16K. In both ...


Parallel Manufacturing Ramp of an SOI-based Microprocessor Chip

2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2007

The challenges of and approaches to a technology transfer of a 90 nm silicon- on-insulator technology in support of a parallel high volume manufacturing ramp are described.


Time optimization of instruction execution in FPGA using embedded systems

2015 International Conference on Futuristic Trends on Computational Analysis and Knowledge Management (ABLAZE), 2015

This paper presents a method to implement time optimization of instructions in Field Programmable Gate Array (FPGA) using application of embedded systems. The proposed technique is intended to reduce the time of processing of instructions inside a processor and ATMega328 microcontroller is used for this purpose. An algorithm has been proposed to predict the most suitable processor architecture which should ...



Educational Resources on Microprocessor chips

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IEEE-USA E-Books

  • Microprocessor design for inteligent point-of-sale terminals

    A point-of-sale (POS) terminal, besides serving as an ordinary isolated cash register, is also part of a retail data collection system. The system emphasis is on data collection, although minimal computational capability is also required. The rate of data input to this system is largely limited by the speed of the operator. These aspects influence terminal design. This article describes the capabilities of an existing terminal processor and compares them to a commercially available microprocessor chip.

  • Why should we do 3D integration?

    3D integration offers a technology that meets the requirements of the current trend in high performance microprocessors. It offers the opportunity to continue the performance trends the industry enjoyed in the past. To take advantage of this opportunity system architecture and design needs to utilize the new possibilities that 3D integration provides.

  • CMOS design of cellular APAPs and FPAPAPs: an overview

    CNN-based analog visual microprocessors have similarities with the so-called Single Instruction Multiple Data systems, although they work directly on analog signal representations obtained through embedded optical sensors and hence do not need a frontend sensory plane or analog-to-digital converters. The architecture of these visual microprocessors is illustrated in the paper through two prototype chips, namely: ACE4K and ACE16K. In both cases, as in other related chips the architecture includes a core array of interconnected elementary processing units, surrounded by a global circuitry.

  • Parallel Manufacturing Ramp of an SOI-based Microprocessor Chip

    The challenges of and approaches to a technology transfer of a 90 nm silicon- on-insulator technology in support of a parallel high volume manufacturing ramp are described.

  • Time optimization of instruction execution in FPGA using embedded systems

    This paper presents a method to implement time optimization of instructions in Field Programmable Gate Array (FPGA) using application of embedded systems. The proposed technique is intended to reduce the time of processing of instructions inside a processor and ATMega328 microcontroller is used for this purpose. An algorithm has been proposed to predict the most suitable processor architecture which should be preferably used to iteratively execute the instructions. This prediction, along with the input of instructions to the FPGA, is done by the microcontroller and the same is transferred to the FPGA using suitable interfacing technique. Two architectures are intertwined and burnt on the microprocessor chip of the FPGA beforehand. Proteus VSM has been used for simulation of the embedded portion of the system and the processor architectures are designed in Xilinx ISE v13.4 and simulated in ISIM simulator.

  • Microprocessor realization of a linear predictive vocoder.

    A microprocessor realization for a linear predictive vocoder is presented. The goal was a low power, low cost, compact special purpose realization of a narrowband speech terminal. The resultant design is a general purpose two bus structure running at a 150 ns cycle time using as the basic signal processing element four of the AMD 2901 CPE chips. This basic structure is augmented by a four cycle multiplier to allow for sufficient signal processing power. The design concessions that mark the LPCM as a special purpose machine designed to be a speech terminal are: limited I/O, and limited memory. The present design requires 162 dual-in-line packages, dissipates less than 45 watts and occupies about 1/3 cubic foot.

  • Chip Off the Old Block

    None

  • A massively parallel systolic array processor system

    The design of a massively parallel processor, comprised of 2304-bit-serial processor elements arranged in a 48 by 48 systolic array, is described. The system consists of the processor array, a microstore controller, and a host computer interface. Program development tools are available on the host computer. The processor array uses 32 NCR GAPP (Geometric Arithmetic Parallel Processor) microprocessor chips, while the microstore controller is implemented with a TMS32010 DSP chip and TTL (transistor-transistor logic) circuitry. Utilizing the nearest neighbor communication capabilities of the GAPP, the array receives data from the host at the south end of the array, outputs data to the host at the north edge of the array, and can wrap data between either the east and west or north and south edges. The array can also be configured as a linear array of 2304 processor elements. The microstore controller interfaces with the host and facilitates downloading of GAPP array machine code, provides for the debugging and monitoring of GAPP array execution from the host, and implements user-defined instructions.<<ETX>>

  • A 32b microprocessor with on chip virtual memory management

    The development of a 140,000 transistor 32b single chip microprocessor, implementing a superminicomputer's 304 instructions will be described. The chip is 8.5 &#215; 8.0mm and dissipates 3W.

  • CBGA package design for C4 PowerPC microprocessor chips: trade-off between substrate routability and performance

    Electrical performance and printed circuit board routability tradeoff are studied in ceramic ball grid array packages (CBGAs). CBGA package design is described for a high speed chip with peripheral drivers. Three general types of array patterns are compared. First, the best routability design, where all the power and ground balls on the CBGA are routed in the center area. Second, a design with four pairs of P/G balls moved to the corners of the CBGA is evaluated, resulting in improvement of electrical performance by 50%, as measured by SSN reduction. The reasons for this improvement are analyzed. Third, even more P/G balls are moved closer to the onchip drivers, achieving an additional 30% reduction in SSN. In each case, the implications on board routability and simultaneous switching noise are assessed.<<ETX>>



Standards related to Microprocessor chips

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No standards are currently tagged "Microprocessor chips"