Conferences related to Design Automation

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2021 IEEE/MTT-S International Microwave Symposium - IMS 2021

The IEEE MTT-S International Microwave Symposium (IMS) is the premier conference covering basic technologies, to passives and actives components to system over a wide range of frequencies including VHF, UHF, RF, microwave, millimeter-wave, terahertz, and optical. The conference will encompass the latest in RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation, wireless systems, RFID and related topics.

  • 2029 IEEE/MTT-S International Microwave Symposium - IMS 2029

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2019 IEEE/MTT-S International Microwave Symposium - IMS 2019

    Comprehensive symposium on microwave theory and techniques including active and passive circuit components, theory and microwave systems.

  • 2018 IEEE/MTT-S International Microwave Symposium - IMS 2018

    Microwave theory and techniques, RF/microwave/millimeter-wave/terahertz circuit design and fabrication technology, radio/wireless communication.

  • 2017 IEEE/MTT-S International Microwave Symposium - IMS 2017

    The IEEE MTT-S International Microwave Symposium (IMS) is the premier conference covering basic technologies, to passives and actives components to system over a wide range of frequencies including VHF, UHF, RF, microwave, millimeter-wave, terahertz, and optical. The conference will encompass the latest in RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation, wireless systems, RFID and related topics.

  • 2016 IEEE/MTT-S International Microwave Symposium - IMS 2016

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2015 IEEE/MTT-S International Microwave Symposium - MTT 2015

    The IEEE MTT-S International Microwave Symposium (IMS) is the premier conference covering basic technologies, to passives and actives components to system over a wide range of frequencies including VHF, UHF, RF, microwave, millimeter-wave, terahertz, and optical. The conference will encompass the latest in RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation, wireless systems, RFID and related topics. The IMS includes technical sessions, both oral and interactive, worksh

  • 2014 IEEE/MTT-S International Microwave Symposium - MTT 2014

    IMS2014 will cover developments in microwave technology from nano devices to system applications. Technical paper sessions, interactive forums, plenary and panel sessions, workshops, short courses, industrial exhibits, and a wide array of other technical activities will be offered.

  • 2013 IEEE/MTT-S International Microwave Symposium - MTT 2013

    The IEEE MTT-S International Microwave Symposium (IMS) is the premier conference covering basic technologies, to passives and actives components to system over a wide range of frequencies including VHF, UHF, RF, microwave, millimeter -wave, terahertz, and optical. The conference will encompass the latest in RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation, wireless systems, RFID and related topics.The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2012 IEEE/MTT-S International Microwave Symposium - MTT 2012

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2011 IEEE/MTT-S International Microwave Symposium - MTT 2011

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2010 IEEE/MTT-S International Microwave Symposium - MTT 2010

    Reports of research and development at the state-of-the-art of the theory and techniques related to the technology and applications of devices, components, circuits, modules and systems in the RF, microwave, millimeter-wave, submillimeter-wave and Terahertz ranges of the electromagnetic spectrum.


2021 26th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA )

ETFA focus is on the latest developments and new technologies in the field of industrial and factory automation. The conference aims to exchange ideas with both industry leaders and a variety of experienced researchers, developers, and practitioners from several industries, research institutes, and academia


2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2020, the 27th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


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Periodicals related to Design Automation

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Automation Science and Engineering, IEEE Transactions on

The IEEE Transactions on Automation Sciences and Engineering (T-ASE) publishes fundamental papers on Automation, emphasizing scientific results that advance efficiency, quality, productivity, and reliability. T-ASE encourages interdisciplinary approaches from computer science, control systems, electrical engineering, mathematics, mechanical engineering, operations research, and other fields. We welcome results relevant to industries such as agriculture, biotechnology, healthcare, home automation, maintenance, manufacturing, pharmaceuticals, retail, ...


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


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Most published Xplore authors for Design Automation

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Xplore Articles related to Design Automation

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Physics-based field-theoretic design automation tools for social networks and web search

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011

Large-scale computations required in the analysis and design of social network interactions and internet search have traditionally had a flavor distinct from EDA. With scale, density, and personalization on the web, the picture is changing. We show early evidence here that EDA-based methodologies in field simulation may show new techniques for search, relevance in online advertising, and social network simulation.


Absynth: A Comprehensive Approach for Full Front to Back Analog Design Automation

2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2018

The benefits of any form of automation are well known, however unlike most other forms of automation, analog design automation (ADA) is not yet accepted by most designers as part of the work-flow. The goal of this work is to explore the needs and the targets to make ADA viable in industry and research. There are various approaches targeting different ...


Data mining based prediction paradigm and its applications in design automation

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Abstract form only given. This talk will review several key challenges in design automation, including areas such as pre-silicon functional verification, design-silicon timing correlation, test cost and quality and describe data mining technologies to implement a prediction platform that provides unique solutions to cover these challenges. Results based on industrial cases will be discussed and other potential applications in design ...


Electronic design automation for social networks

Design Automation Conference, 2010

Online social networks are a growing internet phenomenon: they connect millions of individuals through sharing of common interests, political and religious views, careers, etc. Social networking websites are observing an ever-increasing number of regular users, who rely on this virtual medium to connect with friends and share in the community. As a result, they have become the repository of a ...


Platform-based design automation - Platform Core Compiler

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, 2010

A platform-based design automation methodology is described. The methodology brings advantages that include supporting configurable platform architecture, improving quality of SoC integration and avoiding manual error and shorten SoC integration schedule. A benchmark is also proposed to realize how the methodology can address the targets and meet time-to-market goal.


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Educational Resources on Design Automation

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IEEE-USA E-Books

  • Physics-based field-theoretic design automation tools for social networks and web search

    Large-scale computations required in the analysis and design of social network interactions and internet search have traditionally had a flavor distinct from EDA. With scale, density, and personalization on the web, the picture is changing. We show early evidence here that EDA-based methodologies in field simulation may show new techniques for search, relevance in online advertising, and social network simulation.

  • Absynth: A Comprehensive Approach for Full Front to Back Analog Design Automation

    The benefits of any form of automation are well known, however unlike most other forms of automation, analog design automation (ADA) is not yet accepted by most designers as part of the work-flow. The goal of this work is to explore the needs and the targets to make ADA viable in industry and research. There are various approaches targeting different sets of designers of different experience levels. In this work, we present ABSYNTH, an ADA tool which can be used with or without expert knowledge depending on the interest and proficiency of the user. It also makes use of advanced modeling techniques like Support Vector Regression, and other neural network techniques for learning the circuit models during the initial runs and contribute during repeated runs of the circuit. Four circuits have been presented where automation of different steps have been carried out. three of these circuits have been used in a manufactured chip, that will soon be tested. A generic hybrid layout generator based on a constrained template which can be optimized while maintaining the matched structure has been presented. This improves the quality of the layout by producing results comparable or better than those predicted by simulators without parasitic extraction.

  • Data mining based prediction paradigm and its applications in design automation

    Abstract form only given. This talk will review several key challenges in design automation, including areas such as pre-silicon functional verification, design-silicon timing correlation, test cost and quality and describe data mining technologies to implement a prediction platform that provides unique solutions to cover these challenges. Results based on industrial cases will be discussed and other potential applications in design automation will be explained. In the functional verification space, we will demonstrate an iterative learning framework for reducing simulation costs and improving coverage. This framework is based on two learning components: a novelty test detector and a rule extractor. The novelty test detector is a test selection mechanism that analyzes the tests, produced by the RTPG tool, prior to simulation and identifies the tests that are more likely to hit coverage holes. The rule extractor learns from novel tests identified by novelty detection. The learning is used to refine the test generation process, so the resulting tests programs are more likely to hit coverage holes. The learning framework was evaluated using the simulation infrastructure for a commercial 64-bit, multi-thread micro- processor built in a 28nm node. Based on the evaluation of toggle coverage for the complex fixed integer unit, we demonstrate the ability to reduce the number of test programs by 95%. In addition, we also demonstrate the ability to extract rules from novel test programs. These rules are used to refine test generation, where the resulting tests hit additional known coverage holes. In design-silicon timing correlation, we will show a framework for analyzing design and test data for extracting knowledge that explains unexpected test results. This framework is evaluated using silicon measurements and design data from 30 high-performance dual-core SOCs. Over 2100 paths were measured on each part. For this design, the path measurements behaved differently than the expected values determined by the STA tools as one cluster of paths performed better than expected while another cluster performed worse. Based on the evaluation of this framework, we demonstrate the ability to explain the fast and slow paths by generating simple reasons using the test data. These rules indicate that there is a design issue with a memory controller interface wrapper and these findings were later validated by domain experts. In the parametric tests space, we will show two different parametric tests analysis frameworks for reducing tests costs and improve test quality. The first framework will demonstrate the ability to learn a predictive models from the parametric test data to predict parts that are likely-to- fail after the entire burn-in cycle. This learning framework was evaluated using 8 lots of test data from a burn-in reduction experiment performed on a 3-axis accelerometer. Each lot contains 9k dies and over 500 parametric tests were performed on each device after 10, 24 and 48 hours of burn-in. Based on the evaluation, we demonstrate the ability to identify a large group of parts, ~98% of the total population, that do not require additional burn-in after 10 hours. This suggests that it is possible to save up to 78% in burn-in costs as we can reduce the burn-in time by a factor of 4.8 for most of the parts. The remaining 2% of parts are more susceptible to failing, where this small population includes all parts that fail after the entire burn-in cycle. The second framework will demonstrate the ability to learn from the parametric wafer test data of known customer return and apply these models to seen parts that will become field failures in the future. The learning framework was evaluated using 48 lots wafer probe test data for a high quality SoC from the automotive market. Each lot contained over 12k passing dies and one customer return. More than 1000 parametric tests were performed on each device. The evaluation was formatted in a realistic setting where the learning based on one customer return was applied to only the lots that occurred after the part was returned by the customer. Based on the evaluation of the framework, we show that it is possible to learn from 8 customer returns and apply the learning to screen out 9 other customer returns. Hence, applying this statistical framework in practice would result in the identification of nearly 23% of the 48 customer returns, which would significantly reduce the DPPM rate for these high quality products.

  • Electronic design automation for social networks

    Online social networks are a growing internet phenomenon: they connect millions of individuals through sharing of common interests, political and religious views, careers, etc. Social networking websites are observing an ever-increasing number of regular users, who rely on this virtual medium to connect with friends and share in the community. As a result, they have become the repository of a vast amount of demographic information, which could deliver valuable insights to businesses and individuals. However, as of today, this data is for the most part still untapped, partly because of the complexity entailed by analyzing some of these vast social connectivity graphs. Another area that deals with large data sets is Electronic Design Automation (EDA), the result of increasingly complex computer systems. The powerful tools used to deal with these data sets open many possibilities for social networks. In this work we propose to study interesting aspects of social networks by deploying some of the solutions commonly used in EDA.

  • Platform-based design automation - Platform Core Compiler

    A platform-based design automation methodology is described. The methodology brings advantages that include supporting configurable platform architecture, improving quality of SoC integration and avoiding manual error and shorten SoC integration schedule. A benchmark is also proposed to realize how the methodology can address the targets and meet time-to-market goal.

  • A new approach for electronic design automation of analog building blocks

    Though transistor technology can be produced in channel length smaller than 20nm, analog circuits cannot be designed with small channel length due to non- idealities. Furthermore, in analog circuit design, the design process is challenging due to non-idealities of transistors. Because of the transistor channel length cannot be selected small in analog circuit design, the important performance criteria as power dissipation and chip occupation area must be optimized. Also, the design process must be shortened in the design of analog circuits. In this work, a new approach is proposed for the design automation of symmetrical operational transconductance amplifier. The transconductance (Gm) of OTA is obtained for different size of transistors with 0.18μm TSMC technology in CADENCE environment and a model of transconductance is realized with neural network. The transistor sizes for the desired transconductance is optimized with genetic algorithm.

  • Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach

    This paper presents an innovative methodology to efficiently schedule design automation tasks during the execution of an analog IC layout-aware sizing process. The referred synthesis process includes several sub-tasks such as DC simulation, floorplanning, placement, global routing, parasitic extraction, and circuit simulations in multiple worst case corners. The schedule of the design tasks is here optimized taking into account standard multi-core architectures, tasks dependencies, accurate time estimations for each task and a limited number of licenses for using commercial tools, e.g., number of simulator licenses. The proposed methodology, first, considers a directed acyclic graph for representing the design flow and task dependencies, then, an evolutionary kernel is used to implement a single-objective multi-constraint optimization. The efficiency and impact of the proposed approach is validated by using a state-of-the-art Analog IC design automation environment.

  • The Intel Design Automation System

    The Intel Design Automation (DA) System is overviewed within the framework of Intel's business and technological goals. The philosophies and goals that direct development, acquisition, and deployment of DA capabilities throughout Intel are provided as a foundation for a more detailed discussion of specific areas within the total DA system. The "computing hierarchy" used within Intel world-wide for design and verification of its products is presented, as well as a high-level picture of the entire DA system for Intel's components products mix. With this overview as a basis, detailed explanations of the Engineering Design Environment (EDeN), Functional Design Verification, Hierarchical Layout Verification, and Circuit Performance Verification are presented.

  • Electrical design and design automation for packaging

    One important challenge in the electrical design of electronic packaging is encountered in the many systems requiring processors operating at clock frequencies in the hundreds of Megahertz. The competition to provide higher performance computers results in an increasing number of processors in a system and these processors are running at faster clock frequencies. The package needs to support wider buses at higher frequencies to connect the processors with each other and with cache and main memory data storage. Since the interconnects must run without interruption, the timing and noise characteristics of these paths must be characterized and managed. The short design cycle is supported by including the management of the timing and noise characteristics as an integral part of the high-level system design at the beginning of the project and then verifying that the same constraints are met for the formal design review before the finished designs are released into manufacturing. The principles we follow to design the packaging for multi- processor systems are presented. A methodology for design will be described which defines budgets and equations to efficiently calculate the timing and noise on the interconnects. This provides a means to include the electrical considerations in the optimal cost-performance choice of technology. The budgets and equations are then integrated into the design tools and provide guidance in the design of the power and signal distribution and the means for thorough post-design verification of the electrical performance of the package in the system.

  • Thermal/mechanical design and design automation for packaging

    The need for mechanical and thermal analysis/synthesis is motivated through examples of applications. The development cycle for design is discussed in some detail and the criticality of comprehensive analysis to ensure successful design is discussed. It is demonstrated that successful integration of diverse functional and reliability requirements requires thorough studies of design options. The current state of the art in design synthesis and analysis tools is reviewed. It is suggested that design tools still need improvements in connectivity between electrical layout and thermal and mechanical analysis/synthesis tools. Another issue that needs greater emphasis is the issue of dimensional scale transitions in analyses at the die level vs those at the package and system levels. Both these issues are reviewed in context of the ability of current tools. Some challenges as we go forward are identified based on this review.



Standards related to Design Automation

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IEEE Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks

ALF shall serve as the data specification language of library elements for design applications used to implement integrated circuits. The range of abstraction shall include from the register-transfer level (RTL) to the physical level. The language shall model behavior, timing, power, signal integrity, physical abstraction and physical implementation rules of library elements.


IEEE Standard for Design and Verification of Low Power Integrated Circuits

This standard establishes a format used to define the low power design intent for electronic systems and electronic intellectual property. The format provides the ability to specify the supply network, switches, isolation, retention and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low power design specification and the logic design specification ...


IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std. 1450-1999) for Semiconductor Design Environments

Define structures in STIL to support usage as semiconductor simulation stimulus; including: 1) mapping signal names to equivalent design references, 2) interface between Scan and BIST, and the logic simulation, 3) data types to represent unresolved states in a pattern, 4) parallel or asynchronous pattern execution on different design blocks, and 5) expression-based conditional execution of pattern constructs. Define structures ...


IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process

SDF (Standard Delay Format) is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.


IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language

SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including ...


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