Conferences related to Built-in Test

Back to Top

2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC)

The 2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC 2020) will be held in Metro Toronto Convention Centre (MTCC), Toronto, Ontario, Canada. SMC 2020 is the flagship conference of the IEEE Systems, Man, and Cybernetics Society. It provides an international forum for researchers and practitioners to report most recent innovations and developments, summarize state-of-the-art, and exchange ideas and advances in all aspects of systems science and engineering, human machine systems, and cybernetics. Advances in these fields have increasing importance in the creation of intelligent environments involving technologies interacting with humans to provide an enriching experience and thereby improve quality of life. Papers related to the conference theme are solicited, including theories, methodologies, and emerging applications. Contributions to theory and practice, including but not limited to the following technical areas, are invited.


2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Test Conference (ITC)

International Test Conference, the cornerstone of TestWeek events, is the premier conference dedicated to the electronic test of devices, boards, and systems -- covering the complete cycle from design verification, test, diagnosis, failure analysis, and back to process improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment designers, and test engineers.

  • 2019 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek events, is the premier conference dedicated to the electronic test of devices, boards and systems – covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment designers, and test engineers

  • 2018 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification and validation, test (DFT, ATPG, and BIST), diagnosis, failure analysis and back to process, yield, reliability and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

  • 2017 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek events, is the premier conference dedicated to the electronic test of devices, boards and systems -- covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment designers, and test engineers.

  • 2016 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek events, is the world's premier conference dedicated to the electronic test of devices, boards and systems -- covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment designers, and test engineers.

  • 2015 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek

  • 2014 IEEE International Test Conference (ITC)

    ITC is the world's premier conference dedicated to electronic test technology, covering the complete cycle from design verification, test, diagnosis, failure analysis back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces and learn how these challenges have been addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

  • 2013 IEEE International Test Conference (ITC)

    International Test Conference is the world

  • 2012 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek events, is the world s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, des

  • 2011 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek events, is the world s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers.

  • 2010 IEEE International Test Conference (ITC)

    ITC is the world's premier conference dedicated to electronic test technology, covering the complete cycle from design verification,test, diagnosis, failure analysis back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces and learn how these challenges have been addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

  • 2009 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek(tm) events, is the world's premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers,

  • 2008 IEEE International Test Conference (ITC)

    International Test Conference, the cornerstone of TestWeek(tm), is the world's premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.

  • 2007 IEEE International Test Conference (ITC)

  • 2006 IEEE International Test Conference (ITC)

  • 2005 IEEE International Test Conference (ITC)

  • 2004 IEEE International Test Conference (ITC)

  • 2003 IEEE International Test Conference (ITC)

  • 2002 IEEE International Test Conference (ITC)

  • 2001 IEEE International Test Conference (ITC)

  • 2000 IEEE International Test Conference (ITC)

  • 1999 IEEE International Test Conference (ITC)

  • 1998 IEEE International Test Conference (ITC)

  • 1997 IEEE International Test Conference (ITC)

  • 1996 IEEE International Test Conference (ITC)


2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

The International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) is a forum devoted to modeling, simulation and synthesis for Analog, Mixed-signal, RF (AMS/RF) and multi-domain (MEMs, nanoelectronics, optoelectronics, biological, etc.) integrated circuits and systems. Experiences with modeling, simulation and synthesis techniques in diverse application areas are also welcomed. Objective technologies include CMOS, beyond CMOS, and More-than- Moore such as MEMs, power devices, sensors, passives, etc.


More Conferences

Periodicals related to Built-in Test

Back to Top

Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


More Periodicals

Most published Xplore authors for Built-in Test

Back to Top

Xplore Articles related to Built-in Test

Back to Top

A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution

2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2015

In today's world Built-In Test is the necessity for the designs of digital logic circuits. However, providing solutions with such concept requires cumbersome and typical procedures of designs and because of this majority of the design go without incorporating the features of Built-In Test in the designs. The design procedures further aggravates if optimal design is needed. Hence, in view ...


Empirical mode decomposition based reducing false alarm filter for built-in test signal

2011 IEEE International Instrumentation and Measurement Technology Conference, 2011

False alarm is the phenomenon that built-in test or other detection module indicates fault problem but actually no fault exists. High false alarm rate severely restricts the development of built-in test system. This paper reveals that doing extra processing on the intrinsic mode functions obtained from empirical mode decomposition, we can establish a filter with good performance in reducing false ...


Built-in test design and optimization method based on dependency model

2016 Prognostics and System Health Management Conference (PHM-Chengdu), 2016

A design optimization method based on dependency model is proposed for Built- in test design in Prognostics and Health Management. Firstly, simplify the dependency model, eliminate the redundant test and merge the fuzzy fault model. Secondly identify the minimum test vector matrix to each fault mode. Under the principles of reliability and costs, determine the optimal test vector, which is ...


Simulation of hydraulic brake built-in test system for a certain UAV

Proceedings of the 32nd Chinese Control Conference, 2013

The mathematic models of components for hydraulic pump, brake valve, brake cylinder and so on are established for the hydraulic brake system based on the parameters of a certain unmanned aerial vehicle hydraulic system. According to brake built-in test scheme, the hydraulic brake system is designed and simulated. In order to improve the performance of system, the optimization algorithms of ...


A Complex Electronics System Built-in-Test Based on Time-Triggered CAN Bus

2007 8th International Conference on Electronic Measurement and Instruments, 2007

This paper describes the built-in-test design and analysis of the X-by-wire system named complex electronics system (CES). The components of CES communicate with each other based on the CAN bus with time-triggered schedule, to support deterministic and safety-critical applications. The behavior of all nodes are based on global schedule, global clock synchronization, and mixed of event-triggered with special window in ...


More Xplore Articles

Educational Resources on Built-in Test

Back to Top

IEEE.tv Videos

Computer: Alan Turing at Bletchley Park
Research, Development and Field Test of Robotic Observation Systems for Active Volcanic Areas in Japan
CES 2009: World's First 3-D Webcam
Micro-Apps 2013: Environment Simulation for Counter-IED Jammer Test
5G Wireless A Measurement and Metrology Perspective: MicroApps 2015 - Keysight Technologies
CES 2008: Eye-Fi Card for Wireless Photo Uploads
Micro-Apps 2013: Creating and Analyzing Multi-Emitter Environment Test Signals with COTS Equipment
Micro-Apps 2013: Power Added Efficiency (PAE) Analysis with 8990B Peak Power Analyzer
Raspberry Pi High Speed SerDes Characterization Platform
GeoOrbital E-Wheel Allows Effortless Biking
MicroApps: Implications of Emerging Technologies on Power Amplifer Manufacturing Test Speed (Agilent Technologies)
MicroApps: Fast, Accurate and Nondestructive Solutions of Materials Test up to 1.1 THz (Agilent Technologies)
Testing 5G: OTA and the Connectorless World - IMS 2017
The Era of AI Hardware - 2018 IEEE Industry Summit on the Future of Computing
Alberto Broggi accepts the IEEE Medal for Environmental and Safety Technologies - Honors Ceremony 2017
Panel Session: 5G Test and Measurements - 5G Summit at IMS 2017
Interview with the TX-0 Computer development team
IMS 2012 Microapps - Use of FPGAs for Faster Test Times and Repeatability on Cellular Measurements
Micro-Apps 2013: Precision RF/MW Cable and Antenna Test in the Field
IEEE Region 5 Presents Stepping Stone Awards on the 50th Anniversary of Apollo 11

IEEE-USA E-Books

  • A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution

    In today's world Built-In Test is the necessity for the designs of digital logic circuits. However, providing solutions with such concept requires cumbersome and typical procedures of designs and because of this majority of the design go without incorporating the features of Built-In Test in the designs. The design procedures further aggravates if optimal design is needed. Hence, in view of this, an idea of a heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution is proposed through this paper.

  • Empirical mode decomposition based reducing false alarm filter for built-in test signal

    False alarm is the phenomenon that built-in test or other detection module indicates fault problem but actually no fault exists. High false alarm rate severely restricts the development of built-in test system. This paper reveals that doing extra processing on the intrinsic mode functions obtained from empirical mode decomposition, we can establish a filter with good performance in reducing false alarm rate. Simulations are carried out on steering gear feedback voltage signal of target drone aircraft, and the results show great improvement for built-in test signal to reduce false alarm phenomenon.

  • Built-in test design and optimization method based on dependency model

    A design optimization method based on dependency model is proposed for Built- in test design in Prognostics and Health Management. Firstly, simplify the dependency model, eliminate the redundant test and merge the fuzzy fault model. Secondly identify the minimum test vector matrix to each fault mode. Under the principles of reliability and costs, determine the optimal test vector, which is used as the criterion of fault detection and isolation. Finally transfer the optimal test vector to embedded diagnosis program and download to the Built-in test. Example shows that the method can diagnose the faults with the lowest test costs and the least tests, and improve the level of fault diagnosis design.

  • Simulation of hydraulic brake built-in test system for a certain UAV

    The mathematic models of components for hydraulic pump, brake valve, brake cylinder and so on are established for the hydraulic brake system based on the parameters of a certain unmanned aerial vehicle hydraulic system. According to brake built-in test scheme, the hydraulic brake system is designed and simulated. In order to improve the performance of system, the optimization algorithms of traditional PID and fuzzy adaptive PID are discussed by simulation experiment in Matlab/Simulink. The simulation results prove that the optimization arithmetic of built-in test for hydraulic brake is satisfied.

  • A Complex Electronics System Built-in-Test Based on Time-Triggered CAN Bus

    This paper describes the built-in-test design and analysis of the X-by-wire system named complex electronics system (CES). The components of CES communicate with each other based on the CAN bus with time-triggered schedule, to support deterministic and safety-critical applications. The behavior of all nodes are based on global schedule, global clock synchronization, and mixed of event-triggered with special window in the system matrix period. The test ECU module is designed with ARM9 processor, can support a powerful testing function sets. The experiment and simulation expressed that the built-in-test schema with mixed schedule of CAN bus is a good method to solve the deterministic behavior and guarantee some basic quality of service, even in presence of faults.

  • JTAG/Boundary Scan for Built-In Test

    Poor system reliability, combined with frequent failures of Built-In Test (BIT), may cause crew to undertake missions with undetected faults. Further, the need for rapid field repair, combined with line-replaceable unit (LRU) endemic fault isolation, dictates a new approach to system test. The use of JTAG-based boundary-scan test (BST), embedded on-board without the need for external physical hardware probes, cabling and fixturing, is described to address this issue. This paper details the application of JTAG for BIT, Test Access Port (TAP) controller firmware requirements, BST library Application Program Interface (API), and hardware design requirements.

  • Design and Implementation of an Embedded Diagnosis System for Radar Built-in Test Equipment

    This paper describes a kind of embedded diagnosis expert system for radar built-in test equipment(BITE). Based on gradation diagnosis model and fault separation tree, diagnosis knowledge is represented by integrated framework, and the direct inference, reverse inference and hybrid inference diagnosis strategy are carried out in radar system. Site test results showed that the diagnosis system could improve fault diagnosis accuracy and speed for modern radar fault diagnosis.

  • Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit

    In this paper, an electrical interconnect test method and a built-in test circuit are proposed to detect and locate open defects in a 3D stacked IC made of dies, in which ESD protection circuits are not embedded. The test method is based on quiescent supply current that is made flow through the interconnect to be tested only in the tests. Feasibility of the tests is evaluated by Spice simulation. The simulation results show that open defects in a 3D stacked IC not embedding ESD protection circuits are detected by the test method, like in the tests of ICs embedding ESD protection circuits.

  • Application of Trend Analysis Methodologies on Built-in-Test (BIT) (and non-BIT) Systems in a Operational U.S. Navy Fighter/Attack Squadron

    This paper will outline the process and 'real-world' experience of applying trending techniques to supporting a highly complicated system within a high pressure environment with an extremely low tolerance for errors by improving the corrective and preventative maintenance cycles. The paper will also discuss some of the key benefits realized and challenges encountered in implementing this

  • Built in test and health monitoring for fault tolerant systems

    Deployed test and health monitoring systems must actually manage two tasks: (1) the testing and monitoring the device under test, and (2) the testing and monitoring the test system itself. The ability to isolate and identify faults is crucial to deployed test and health monitoring systems. Understanding failure mechanisms provides invaluable insight regarding whether the device under test is, in fact, the failure, or if something in the test and monitoring system is faulty: the sensor, the hardware, or the interconnect/cabling system. Efficiently and effectively isolating marginal components or interconnects can save hours of costly product analysis, system downtime, and test efforts, and in extreme cases, it can also save lives. This white paper reviews technology used on two separate projects: 1) remote health and safety monitoring of hybrid bus fleets, and 2) remote fault monitoring of DAQ/Control units.



Standards related to Built-in Test

Back to Top

IEEE Standard for a Broad-Based Environment for Test (ABBET(TM)), Overview and Architecture

ABBET will provide standards for an integrated environment, realizing the capabilities of test related standards including, at a minimum, active standards sponsored by the IEEE Standards Coordinating Committee 20. The ABBET family of standards consists of a base standard and a series (P1226.1, etc.) of componet standards and guides. This PAR is for the base standard which represents an overview ...


IEEE Standard for a Mixed-Signal Test Bus

Interface system between mixed-signal electronic components, assemblies, and systems, and external or built-in-test equipment to provide those components, assemblies, and systems with testability attributes.


IEEE StandardTest Interface Language (STIL) for DigitalTest Vector Data

This standard defines a test description language that: a) Facilitates the transfer of large volumes of digital test vector data from CAE environments to automated test equipment (ATE) environments; b) Specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a device under test (DUT); c) Supports the volume of test vector data generated ...


Standard for Describing On-Chip Scan Compression

This standard defines how the necessary information is passed from scan insertion to pattern generation and from pattern generation to diagnosis such that different tool vendors could be used for each step independent of on-chip scan compression logic used.


Standard Test Access Port and Boundary Scan Architecture

This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to - testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate; - testing the integrated circuit itself; and - observing or modifying circuit activity during the component's normal operation. The test logic consists ...


More Standards

Jobs related to Built-in Test

Back to Top