Conferences related to Timing Circuits And Clock Generators

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.


2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation


2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting

The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science


2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

The IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in the area of asynchronous design.



Periodicals related to Timing Circuits And Clock Generators

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems Magazine, IEEE



Most published Xplore authors for Timing Circuits And Clock Generators

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Xplore Articles related to Timing Circuits And Clock Generators

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Power-Supply and Substrate-Noise-Induced Timing Jitter in Nonoverlapping Clock Generation Circuits

IEEE Transactions on Circuits and Systems I: Regular Papers, 2008

This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The ...


An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2001

A simple, yet effective, approach to the generation of switches' control signals to reduce timing-skew problems in interleaved and double-sampled switched-capacitor circuits is proposed. The new approach, unlike similar methods previously proposed, avoids the introduction of additional switches in the switched-capacitor circuits, at the cost of a minor increase of complexity in the clock phase generation. This has two main ...


A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007

A clock generator fabricated in 90nm CMOS occupies 300times128mum<sup>2</sup> die area and dissipates 40mW at 1.2V. An interleaved clock-edge control technique extends the frequency tuning range and enables control of both rising and falling edge timing. A clock-period dithering technique enhances frequency tuning resolution. Disturbance-control functions that control jitter, duty cycle, and clock skew make timing margin testing possible


A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS

2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

This paper presents a crystal-less programmable clock generator. The programmable clock generator takes advantages of both RC and LC oscillators. The frequency reference is generated by the RC oscillator without using expensive external crystals. The sawtooth signal generated from the RC oscillator is sampled by low phase-noise differential clocks which are divided from the LC oscillator. The timing information is ...


A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004

This paper presents a comprehensive analysis of mismatch-insensitive clock generation techniques for general parallel sampled-data systems. Two jitter- insensitive clock generation schemes are described, a class of multi-purpose, low-jitter, multi-phase clock generator platform is proposed. The platform can provide clock phases for the two pre-described clock generation schemes and has the advantages of being insensitive to timing mismatches, having a ...



Educational Resources on Timing Circuits And Clock Generators

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IEEE.tv Videos

ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS
SOC DESIGN METHODOLOGY FOR IMPROVED ROBUSTNESS
IEEE Custom Integrated Circuits Conference
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
A Spike-Timing Neuromorphic Architecture: IEEE Rebooting Computing 2017
Alice Wang - SSCS Chip Chat Podcast, Episode 6
Generating Stochastic Bits Using Tunable Quantum Systems - Erik Blair at INC 2019
26th Annual MTT-AP Symposium and Mini Show - Dr. Ajay Poddar
Spike Timing, Rhythms, and the Effective Use of Neural Hardware
Maker Faire 2008: Spectrum's Digital Clock Contest Winner
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
THz Transistors: Present and Future
A Precision 140MHz Relaxation Oscillator in 40nm CMOS with 28ppm/C Frequency Stability for Automotive SoC Applications: RFIC Interactive Forum 2017
Starting Your Own Company - The Challenges and the Rewards
2017 IEEE Donald O. Pederson Award in Solid-State Circuits: Takao Nishitani and John S. Thompson
Kurt Petersen: 2019 IEEE Medal of Honor Recipient
Interview with Takao Nishitani - IEEE Donald O. Pederson Award in Solid-State Circuits Co-Recipient 2017
Evolution of Optical and Transport Technologies for 5G Crosshaul Networks - IEEE Future Networks Initiative webinar
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic: IEEE Rebooting Computing 2017
Design and Comparison of Crosstalk Circuits at 7nm - Md Arif Iqbal - ICRC San Mateo, 2019

IEEE-USA E-Books

  • Power-Supply and Substrate-Noise-Induced Timing Jitter in Nonoverlapping Clock Generation Circuits

    This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mum CMOS process parameters, and a reference simulation in 0.18 mum is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mum process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.

  • An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits

    A simple, yet effective, approach to the generation of switches' control signals to reduce timing-skew problems in interleaved and double-sampled switched-capacitor circuits is proposed. The new approach, unlike similar methods previously proposed, avoids the introduction of additional switches in the switched-capacitor circuits, at the cost of a minor increase of complexity in the clock phase generation. This has two main advantages. First, the performance degradation due to the additional switch is avoided. Second, it becomes extremely easy to build interleaved architectures combining preexisting analog blocks.

  • A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability

    A clock generator fabricated in 90nm CMOS occupies 300times128mum<sup>2</sup> die area and dissipates 40mW at 1.2V. An interleaved clock-edge control technique extends the frequency tuning range and enables control of both rising and falling edge timing. A clock-period dithering technique enhances frequency tuning resolution. Disturbance-control functions that control jitter, duty cycle, and clock skew make timing margin testing possible

  • A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS

    This paper presents a crystal-less programmable clock generator. The programmable clock generator takes advantages of both RC and LC oscillators. The frequency reference is generated by the RC oscillator without using expensive external crystals. The sawtooth signal generated from the RC oscillator is sampled by low phase-noise differential clocks which are divided from the LC oscillator. The timing information is then amplified by the sampler which uses hysteresis. An additional block, gain adjuster (GA), reduces lock time and dithering. After the system gets locked, it achieves 0.01 %/V and 25.5 ppm/°C frequency variations for 100 MHz generated clock. The 14 nm FinFET CMOS programmable clock generator draws 28 mA current from a single 1.8 V supply and occupies an active area of 0.12 mm2, It achieves 163 dBc/Hz FoM for 100 MHz test clock.

  • A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems

    This paper presents a comprehensive analysis of mismatch-insensitive clock generation techniques for general parallel sampled-data systems. Two jitter- insensitive clock generation schemes are described, a class of multi-purpose, low-jitter, multi-phase clock generator platform is proposed. The platform can provide clock phases for the two pre-described clock generation schemes and has the advantages of being insensitive to timing mismatches, having a simple and highly robust architecture such that the clock generator can be generalized not only for an arbitrary number N of time-interleaved (TI) paths, but also can be applied to general TI sampled data systems including ADCs, DACs and N-path filters.

  • Power-Supply Noise Attributed Timing Jitter in Nonoverlapping Clock Generation Circuits

    This paper describes an analysis of timing jitter induced by power-supply noise in nonoverlapping clock generation circuits typically used in switched- capacitor sigma-delta modulators. Substrate noise effects are also included but not treated as a separate phenomenon since the MOSFET bulk contacts are connected to the power-supply or ground. Two different nonoverlapping clock generation circuits have been compared and treated independently: the NOR based and the NAND based architectures. Furthermore, all possible connection topologies of the circuit blocks in the clock generation circuits are investigated. Monte Carlo simulations have been performed in Spectre at BSIM3v3 transistor model level using parameters from a 0.18mum process to show which of the topologies is most suitable as clock generator for wideband applications. In terms of timing jitter sensitivity to power-supply noise, the NOR based architecture is slightly more robust and suitable for providing a timing reference to a sampling circuit

  • A direct-skew-detect synchronous mirror delay for application-specific integrated circuits

    A nonfeedback CMOS digital-clock-generator, direct-skew-detect synchronous- mirror-delay (direct SMD) circuit has been developed that achieves clock-skew suppression in only two clock cycles for application-specific integrated circuits having unfixed and various clock paths. The direct SMD circuit detects both clock skew and clock cycle by using a direct-skew detector and clock-suspension circuitry. The skew-detection scheme removes the phase errors caused by delay in the clock-driver circuit. Measurements demonstrated that the direct SMD circuit eliminates various amounts of clock skew (2.0-3.0 ns) at 200 MHz in two clock cycles.

  • Digital multiphase clock/pattern generator

    In telecommunications systems, the commonly used method to generate clocks is based on phase-locked loop or delay-locked loop related frequency synthesis. In this paper, we address a method of digital multiphase clock/pattern generation (MPCG) to generate a system clock or pulse pattern vector when a multiphase clock is available. The advantages of the multiphase clock method are: (a) the design method is digital; (b) the working frequency range is very wide; and (c) the sensitivity to noise is less than analog methods. Different approaches to implement the basic blocks in MPCG are described. A design example implemented in BiCMOS uses eight clock phases at 622 MHz obtained by dividing a 5-GHz clock to generate a clock at 622 MHz/spl times/32/53=376 MHz. By such a method, we can generate a pulse pattern vector as well. The maximum time resolution is equal to half of the phase difference. A low power solution is achieved without loss of circuit speed.

  • On-Chip Circuit for Measuring Data Jitter in the Time or Frequency Domain

    An on-chip data jitter measurement circuit in 0.11-μm CMOS is demonstrated. It utilizes a data-to-clock converter, pulse generators, and an integrator followed by a sample-&-hold. The circuit outputs a data jitter waveform in real-time, and doesn't require a reference clock. Its measurement linearity is 11_μ_V/ps with an error of 1.56 psRMSfor a 2.5 Gbps 7-stage PRBS.

  • PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor

    Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 mu m BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz.<<ETX>>



Standards related to Timing Circuits And Clock Generators

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No standards are currently tagged "Timing Circuits And Clock Generators"