Conferences related to Radiation Hardened

Back to Top

2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)

The conference will provide a forum for discussions and presentations of advancements inknowledge, new methods and technologies relevant to industrial electronics, along with their applications and future developments.


2019 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


2019 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

This conference is the annual premier meeting on the use of instrumentation in the Nuclear and Medical fields. The meeting has a very long history of providing an exciting venue for scientists to present their latest advances, exchange ideas, renew existing collaboration and form new ones. The NSS portion of the conference is an ideal forum for scientists and engineers in the field of Nuclear Science, radiation instrumentation, software engineering and data acquisition. The MIC is one of the most informative venues on the state-of-the art use of physics, engineering, and mathematics in Nuclear Medicine and related imaging modalities, such as CT and increasingly so MRI, through the development of hybrid devices


2019 Optical Fiber Communications Conference and Exhibition (OFC)

The Optical Fiber Communication Conference and Exhibition (OFC) is the largest global conference and exhibition for optical communications and networking professionals. For over 40 years, OFC has drawn attendees from all corners of the globe to meet and greet, teach and learn, make connections and move business forward.OFC attracts the biggest names in the field, offers key networking and partnering opportunities, and provides insights and inspiration on the major trends and technology advances affecting the industry. From technical presentations to the latest market trends and predictions, OFC is a one-stop-shop.


More Conferences

Periodicals related to Radiation Hardened

Back to Top

Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


More Periodicals

Most published Xplore authors for Radiation Hardened

Back to Top

Xplore Articles related to Radiation Hardened

Back to Top

A Radiation Hardened SRAM in 180-nm RHBD Technology

2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing, 2013

A 24 kB radiation hardened static random access memory using 180-nm commercial CMOS process appropriate for embedded system on a chip integrated circuits is presented. Radiation-hardened design is realized in the system, circuit and layout design to improve tolerance of radiation effects. The proto chips of SRAM are fabricated and tested, not only the electrical properties of SRAM chips are ...


A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications

2017 18th International Symposium on Quality Electronic Design (ISQED), 2017

This paper presents a novel memory cell design as a variant of Lior Atias' 13T cell (mentioned as LA13T cell in this paper) for low-voltage operation and ultra-low power space applications. Using C-element as a replacement of dual- driven inverters in the LA13T cell, our proposed radiation hardened by design memory cell (referred to as RHD13T) can effectively block the ...


Development of a radiation-hardened 0.18 µm CMOS standard cell library for space applications

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014

The radiation-hardened standard cell library can greatly improve the life-time and reliability of ASICs used in space applications. In this paper, we have discussed several radiation-hardened techniques, and have used SPICE simulation to validate these approaches. Finally, using these RH techniques, we have developed a radiation-hardened standard cell library based on 0.18 μm CMOS technology.


Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology

2015 19th International Symposium on VLSI Design and Test, 2015

Radiation Hardened By Design (RHBD) combinational circuits/primitive gates using 0.18um CMOS Technology is developed for Space application with help of Cogenda TCAD software suite. The proposed combinational cells are investigated for radiation simulation using three dimensional (3D) device structure. Single Event Transient (SET) caused by proton, α particle and heavy ions like C, Ar and Kr is observed on developed ...


Radiation hardened by design techniques to mitigating P-hit single event transient

2016 IEEE International Nanoelectronics Conference (INEC), 2016

As technologies scale down in size, the single event effect has become a universal phenomenon. In this work, a new radiation hardened by design (RHBD) technique has been proposed to mitigating P-hit single event transient. This method is named here as the 3 transistor common drain (3TCD) method. With simulations of the inverter chain using a three-dimensional (3D) technology computer-aided ...


More Xplore Articles

Educational Resources on Radiation Hardened

Back to Top

IEEE-USA E-Books

  • A Radiation Hardened SRAM in 180-nm RHBD Technology

    A 24 kB radiation hardened static random access memory using 180-nm commercial CMOS process appropriate for embedded system on a chip integrated circuits is presented. Radiation-hardened design is realized in the system, circuit and layout design to improve tolerance of radiation effects. The proto chips of SRAM are fabricated and tested, not only the electrical properties of SRAM chips are measured, but also the total ionizing dose effects experiments are finished using a Co-60 gamma radiation source. The experimental results show that, the TID(total ionizing dose effect) tolerance of SRAM chips is larger than 300 krad (Si) in which the electrical functions of SRAM are correct, but with the increase of TID rate, the static and dynamic current of SRAM increase seriously, and the write and read time increase slowly. Furthermore, it is verified by our research that, CMOS transistor layout design with ring-gate and P-type guard ring can enhance the TID tolerance of SRAM greatly.

  • A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications

    This paper presents a novel memory cell design as a variant of Lior Atias' 13T cell (mentioned as LA13T cell in this paper) for low-voltage operation and ultra-low power space applications. Using C-element as a replacement of dual- driven inverters in the LA13T cell, our proposed radiation hardened by design memory cell (referred to as RHD13T) can effectively block the unwanted paths from Vdd to Gnd during SEU occurrence, while the problem will be appeared on LA13T cell. Simulation results show that, at the expense of an increased area for obtaining the same drive capability as LA13T cell at each internal store node, RHD13T cell shows better power consumption than LA13T cell during SET occurrence.

  • Development of a radiation-hardened 0.18 µm CMOS standard cell library for space applications

    The radiation-hardened standard cell library can greatly improve the life-time and reliability of ASICs used in space applications. In this paper, we have discussed several radiation-hardened techniques, and have used SPICE simulation to validate these approaches. Finally, using these RH techniques, we have developed a radiation-hardened standard cell library based on 0.18 μm CMOS technology.

  • Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology

    Radiation Hardened By Design (RHBD) combinational circuits/primitive gates using 0.18um CMOS Technology is developed for Space application with help of Cogenda TCAD software suite. The proposed combinational cells are investigated for radiation simulation using three dimensional (3D) device structure. Single Event Transient (SET) caused by proton, α particle and heavy ions like C, Ar and Kr is observed on developed Cells and SET pulse width is measured on primitive gates. The proposed C element based radiation hardened Inverter is simulated using α, Ar and proton energetic particle. Proposed NOR and NAND gates are simulated under the radiation of proton, α and Kr and Single Event Transient Pulse Width is measured.

  • Radiation hardened by design techniques to mitigating P-hit single event transient

    As technologies scale down in size, the single event effect has become a universal phenomenon. In this work, a new radiation hardened by design (RHBD) technique has been proposed to mitigating P-hit single event transient. This method is named here as the 3 transistor common drain (3TCD) method. With simulations of the inverter chain using a three-dimensional (3D) technology computer-aided design (TCAD) simulation tool, it has been found that this new 3TCD method has an obvious effect on the p-channel metal-oxide semiconductor field-effect transistor (PMOS FET) by mitigating single event transient (SET) pulse widths (W<sub>SET</sub>).

  • A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillator

    This paper presents a radiation-hardened-by-design (RHBD) phase-locked loop (PLL) which utilizes a feedback voltage controlled oscillator (FBVCO) to mitigate a single event transient (SET) strike. Whenever the SET pulse attacks the input control voltage of VCO, VCO gives rise to a frequency disturbance and PLL produces a huge jitter at the output clock. The proposed FBVCO consists of an open loop VCO, an integrator and a switched-capacitor resistor. The input transfer function of the FBVCO has a low-pass characteristic so that the FBVCO can reduce any perturbation at the input control voltage. In addition, the proposed RHBD PLL reduces size by using one loop filter (LF) and charge pump (CP) compared to prior works. We simulate the proposed scheme in 130 nm low power CMOS technology at 1.5V supply. The output frequency variation of the proposed PLL from the SET strike is 75% smaller than that of previous PLL at 300 MHz. This RHBD PLL consumes 6.2 mW at 400 MHz output frequency.

  • Radiation Hardened by Design RF Circuits Implemented in 0.13 <formula formulatype="inline"><tex>$\mu$</tex></formula>m CMOS Technology

    Two important RF building blocks, a low noise amplifier and a voltage- controlled oscillator, were designed and fabricated in a 0.13 mum CMOS process using radiation-hardened by design techniques. Both circuits exhibit only minimal degradation with total dose when the parts are irradiated up to 500 krad (SiO2). Laser beam testing results indicate that the output spectrum of the two circuits has no noticeable change with laser energy up to 200 pJ

  • The radiation-hardened BiJFet differential amplifiers with negative current feedback on the common-mode signal

    The article considers the advanced two-stage architectures of the differential op-amps and differential difference operational amplifiers, realized on the base BiJFet of array chips AGAMC1.3, AGAMC2.1 (OJSC “Integral”, Minsk). The suggested circuits provide the higher voltage gain (more than 90...100 dB), and also the low offset voltage (less than 100 μV) over the temperature range -80°C - +80°C, the neutron flux up to 1013n/cm2, and the accumulated dose of radiation up to 3 Mrad. The mathematical justification of the main parameters is given. The results of their computer simulation are presented.

  • Studying the Variation Effects of Radiation Hardened Quatro SRAM Bit-Cell

    Quatro is one of promising SRAM bit-cells for severe radiation environment such as space. However, our study shows that under process and temperature variations of 65nm CMOS, Quatro suffers from high write failure probability, impeding the application of this SRAM bit-cell. We explore the possibility of several popular techniques, such as boosted word-line voltage and negative or boosted bit-line biasing, to improve the write stability of Quatro. We observe that this SRAM bit-cell has different write mechanism from that of the 6T SRAM. Hence, the negative bit-line biasing does not make significant achievement, unlike the 6T SRAM. In this work, we employ the boosting of both word-line and bit-line. By applying 100 mV raised voltage, we obtain robust write operations up to 250 MHz frequency.

  • Designing radiation hardened CMOS microelectronic components at commercial foundries: space and terrestrial radiation environments and device and circuit techniques to mitigate radiation effects

    Summary form only given. When using microelectronic components in a radiation environment, such as those experienced by components in space, components used in nuclear reactors and components used for high-energy physics experiments, specific degradation mechanisms must be mitigated to assure proper component performance over the lifetime of the part. Over the last thirty years, the preferred method for fabricating radiation-hardened parts has been by using boutique, dedicated foundries with specialized processes. The approach is often referred to as hardening-by-process. However, due to the small demand for radiation-hardened components and the exponentially increasing costs of advancing along Moore's, the number of these dedicated foundries has decreased dramatically and they remain more than three generations behind state-of-the- art CMOS. Recently, a novel approach for fabricating radiation-hardened components at commercial CMOS foundries has been developed. In this approach, radiation hardness is designed into the component using non-standard transistor topologies, the addition of guard rings and the application of novel circuit techniques. This presentation began with a description of the space and terrestrial radiation environments, followed by a discussion on the effects of different radiation sources on CMOS technologies. This included a discussion on total-ionizing dose, single-event upsets, single-event latchup and single-event transient radiation effects. Specific non-standard transistor topologies and the application of guard bands to mitigate total dose effects were discussed. Circuit approaches to mitigating single-event effects were also presented. The application of these design approaches does not come without area and performance penalties, which were quantified as part of this presentation. Unique reliability issues associated with the application of hardness-by-design methodologies were also discussed. Finally, a discussion on mitigating terrestrial radiation effects was presented.



Standards related to Radiation Hardened

Back to Top

No standards are currently tagged "Radiation Hardened"


Jobs related to Radiation Hardened

Back to Top