Conferences related to Hi K Metal Gate

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2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2019 IEEE Custom Integrated Circuits Conference (CICC)

Conference with technical sessions, educational sessions, panel discussions and forums.


2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

EDSSC provides as a multidisciplinary forum for the exchange of ideas, research results, and industry experience in the broad areas of electron devices and solid state circuits and systems. The technical program includes invited talks by famous scientists and contributed papers.


2019 Silicon Nanoelectronics Workshop (SNW)

-Sub-10 nm transistors employing conventional and novel architecture including non-classical structures, novel channel and source/drain materials, non-thermal injection mechanisms- Device physics of nanodevices including quantum effects, nonequilibrium and ballistic transport- Modeling and simulation of nanoscale devices- Device scaling issues including doping fluctuations and atomic granularity- Novel devices and architectures for quantum and neuromorphic computing - Optoelectronics using silicon nanostructures- Devices for heterogeneous integration on silicon, including 2D materials, Ge and III-V, CNT, spin-based devices, MEMS and NEMS- Environmental devices which contributes to low-carbon society (wireless sensors, energy harvesters, steep slope devices)


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Periodicals related to Hi K Metal Gate

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Display Technology, Journal of

This publication covers the theory, design, fabrication, manufacturing and application of information displays and aspects of display technology that emphasize the progress in device engineering, device design, materials, electronics, physics and reliabilityaspects of displays and the application of displays.


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Xplore Articles related to Hi K Metal Gate

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High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

2008 IEEE International Electron Devices Meeting, 2008

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on ...


Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications

2015 IEEE International Reliability Physics Symposium, 2015

We explore the use of oxygen vacancies for nonvolatile data storage by trapping electrons in the high-k, gate dielectric layer of NFETs. Programming is performed via channel carrier injection and is erased by tunneling. 64Kb arrays were constructed and reliability is demonstrated.


A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

2008 IEEE Asian Solid-State Circuits Conference, 2008

This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode ...


Chemical mechanical polish: The enabling technology

2008 IEEE International Electron Devices Meeting, 2008

Chemical mechanical polishing (CMP) has traditionally been considered an enabling technology. CMP was first used in the early 1990s for BEOL metallization to replanarize the wafer substrate thus enabling advanced lithography which was becoming ever more sensitive to wafer surface topography. Subsequent uses of CMP included density scaling via shallow trench isolation and interconnect formation via copper CMP. As silicon ...


A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-Κ Metal Gate CMOS

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

This paper describes a low-power Intel* Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) and Ultra- Mobile PCs (UMPC) where average power consumed is in the order of a few hundred mW (as measured by MobileMark'05 OP @ 60 nits brightness) with performance similar to mainstream Ultra-Mobile PCs. The design consists of an in-order pipeline capable of issuing ...


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Educational Resources on Hi K Metal Gate

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IEEE-USA E-Books

  • High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

    For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

  • Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications

    We explore the use of oxygen vacancies for nonvolatile data storage by trapping electrons in the high-k, gate dielectric layer of NFETs. Programming is performed via channel carrier injection and is erased by tunneling. 64Kb arrays were constructed and reliability is demonstrated.

  • A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

    This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm<sup>2</sup> manufactured in a 9-metal 45 nm CMOS process. Thermal design power (TDP) consumption is measured at 2 W, 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz.

  • Chemical mechanical polish: The enabling technology

    Chemical mechanical polishing (CMP) has traditionally been considered an enabling technology. CMP was first used in the early 1990s for BEOL metallization to replanarize the wafer substrate thus enabling advanced lithography which was becoming ever more sensitive to wafer surface topography. Subsequent uses of CMP included density scaling via shallow trench isolation and interconnect formation via copper CMP. As silicon devices scale to 45 nm and beyond however, a large number of new uses of CMP are considered attractive options to enable new transistor technologies. These new uses will demand improved CMP performance (uniformity, topography, low defects) at lower cost which will in turn require breakthroughs in hardware, software, metrology and materials (slurry, pad, cleaning chemicals). This paper reviews the module level and integration challenges of applying traditional CMP steps to enable Hi-K metal gate for 45 nm technology and to advance Cu metallization from 65 nm to 45 nm node. These challenges are then considered with respect to new CMP applications considered for 32 nm and beyond.

  • A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-Κ Metal Gate CMOS

    This paper describes a low-power Intel* Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) and Ultra- Mobile PCs (UMPC) where average power consumed is in the order of a few hundred mW (as measured by MobileMark'05 OP @ 60 nits brightness) with performance similar to mainstream Ultra-Mobile PCs. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data LI caches, independent integer and floating point execution units, x86 front end execution unit, a 512KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 M transistors in a die size under 25 mm2manufactured in a 9-metal 45nm CMOS process with optimized transistors for low leakage packaged in a Halide-Free 441 ball, 14x13 mm2muFCBGA. Thermal Design Power (TDP) consumption is measured at 2 W using a synthetic power-virus test at a frequency of 2 GHz.

  • The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family

    The next generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64 bit Haswell cores, 45 MB L3 cache, 4 DDR4-2133 MHz memory channels, 40 8 GT/s PCIe lanes, and 40 9.6 GT/s QPI lanes. The processor has 5.56 B transistors on a 31.9 mm × 20.8 mm die in Intel's Hi-K metal-gate tri-gate 22 nm CMOS technology with 11 metal layers and achieves up to 33% performance boost. The design supports a wide range of configurations including thermal design power ranging from 55 to 160 W and frequencies ranging from 1.6 to 3.7 GHz. Key architectural innovations include the addition of AVX2 technology, DDR4, and fully integrated voltage regulators (FIVR) that enable per core p-states and uncore frequency scaling.

  • A 22 nm 15-Core Enterprise Xeon® Processor Family

    This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to reduce power consumption. The clock distribution uses a single PLL per column to save power and minimize deskew crossing points. Integrated PCIe Gen3 and Quick Path Interconnect® (QPI) ports operate at 8GT/s. The 4-channel memory interface supports both 1866 MT/s DDR3 and a new memory buffer interface running at 2667 MT/s on the same pins. The core, cache and I/O recovery techniques improve manufacturing yields and enable multiple product flavors from the same silicon die.

  • Session 27: CMOS devices and technology - advanced CMOS logic and SoC platforms

    This session features advanced CMOS platform papers, ranging from 45nm to 22nm, and covering high performance, low power, bulk and SOI technologies. The first paper will present the world's smallest SRAM cell using 22nm technology. The next two papers will present state-of-the-art 32nm platform covering low power and high performance applications. The fourth paper will introduce the first ever 45nm SoC technology using Hi-k/metal gate process. The next paper presents a high density 40nm CMOS technology designed for mobile and wireless applications. The two last papers will present 45nm SOI technologies: one will present Hi-k/Metal Gate integration and the other features optimized asymmetric transistors.

  • Session 16: Process technology - Ge-Channel CMOS and advanced gate stacks

    The first paper describes Ge-Channel MOSFETs with S/D formed by metal-induced dopant activation. The second paper describes interface engineering and characterization of Hi-K in Ge MOSFET with 1nm EOT. The third paper relates to fabrication of ultra-thin GeOI MOSFETs. The fourth paper describes InGaAs MOSFETs with in-situ PH3 surface plasma passivated HfAlO/TaN and HfO<inf>2</inf>/TaN gate stacks. The fifth paper in this session describes Fluorinated HfO2 gate stacks for CMOS for improved reliability. The last paper relates to control of threshold voltage variability in Hi-k-metal Gate stacks through control of grain size and crystallinity in metal gates.

  • Power reduction schemes in next generation Intel® ATOM<sup>™</sup>processor based sOc for handheld applications

    Lincroft, the next generation Intel®ATOM™processor based SoC specifically designed for smartphones, is fabricated in 45 nm Hi-K metal gate CMOS. As part of the extensive low power methodology, the chip is divided into numerous power domains with on die distributed powergates to reduce both active and standby power. Measured data shows upto 50X reduction in standby power. Silicon data shows dramatically low power in sleep and deeper sleep standby power states.



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