Conferences related to Oxide Reliability

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


2019 20th International Symposium on Quality Electronic Design (ISQED)

20th International Symposium on Quality Electronic Design (ISQED 2019) is the premier interdisciplinary and multidisciplinary Electronic Design conference?bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve design quality.


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Periodicals related to Oxide Reliability

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Display Technology, Journal of

This publication covers the theory, design, fabrication, manufacturing and application of information displays and aspects of display technology that emphasize the progress in device engineering, device design, materials, electronics, physics and reliabilityaspects of displays and the application of displays.


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


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Most published Xplore authors for Oxide Reliability

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Xplore Articles related to Oxide Reliability

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Gate oxide reliability improvement for CMOS and MEMS monolithic integration

2012 IEEE International Reliability Physics Symposium (IRPS), 2012

Monolithic integration of 0.18μm 1.8/3.3V CMOS and Micro Electro Mechanical Systems (MEMS) was developed by CMOS first/MEMS last scheme (CMOS-MEMS). During process development, gate oxide reliability is a major concern which can be observed due to (1) electrostatic charge damage through bonding pads during the die sawing stage of MEMS cap formation and (2) plasma induced damage (PID) during MEMS ...


A new degradation mechanism of gate oxide reliability due to "extrinsic" responses of Qbd along rough "bird's-beak" frontline

2011 IEEE International Integrated Reliability Workshop Final Report, 2011

The roughness of "bird's-beak" frontline prior to gate oxidation has been revealed for the first time to degrade gate oxide reliability in TDDB. This new mechanism identifies the "extrinsic" Qbdresponses to electrical fields. The restorations of intrinsic Qbdhave been realized by post-fabrication anneals or process improvement.


Calculating the error in long term oxide reliability estimates

2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167), 2001

Ultra-thin oxide reliability is a critical issue in integrated circuit scaling. Oxide reliability may actually prevent future scaling of SiO/sub 2/ gate dielectrics. The statistical error in long term oxide reliability projections has not been cohesively treated. Using Monte Carlo techniques, the amount of uncertainty in reliability projections is calculated. Applying the derived results to typical published data, the uncertainty ...


Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process

IEEE Transactions on Device and Materials Reliability, 2008

The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low- voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the dc stress, ac stress with dc offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain ...


A unified gate oxide reliability model

1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296), 1999

Existing literature indicates that there are two major mechanisms involved in the time dependent dielectric breakdown (TDDB) of silicon dioxide, and each mechanism dominates under different stress conditions. We suggest that the thermochemical (linear E) model and the hole-induced (1/E) model can be unified in one model. Based on the unified model, a wide range of TDDB data from different ...


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Educational Resources on Oxide Reliability

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IEEE-USA E-Books

  • Gate oxide reliability improvement for CMOS and MEMS monolithic integration

    Monolithic integration of 0.18μm 1.8/3.3V CMOS and Micro Electro Mechanical Systems (MEMS) was developed by CMOS first/MEMS last scheme (CMOS-MEMS). During process development, gate oxide reliability is a major concern which can be observed due to (1) electrostatic charge damage through bonding pads during the die sawing stage of MEMS cap formation and (2) plasma induced damage (PID) during MEMS deep via etch and MEMS pattern etching. Electrostatic charge damage can be much improved by reducing the die sawing time, optimizing die saw cleaning recipe, and removing the pad oxide before MEMS cap formation. An electrostatic charge model has been developed to explain the gate oxide reliability characteristics. PID can be minimized through gated diode or P/N junction diode protection to provide another effective approach for electrical shielding of the MEMS device in our prior work [1].

  • A new degradation mechanism of gate oxide reliability due to "extrinsic" responses of Qbd along rough "bird's-beak" frontline

    The roughness of "bird's-beak" frontline prior to gate oxidation has been revealed for the first time to degrade gate oxide reliability in TDDB. This new mechanism identifies the "extrinsic" Qbdresponses to electrical fields. The restorations of intrinsic Qbdhave been realized by post-fabrication anneals or process improvement.

  • Calculating the error in long term oxide reliability estimates

    Ultra-thin oxide reliability is a critical issue in integrated circuit scaling. Oxide reliability may actually prevent future scaling of SiO/sub 2/ gate dielectrics. The statistical error in long term oxide reliability projections has not been cohesively treated. Using Monte Carlo techniques, the amount of uncertainty in reliability projections is calculated. Applying the derived results to typical published data, the uncertainty in the failure rate is greater than an order of magnitude.

  • Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process

    The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low- voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the dc stress, ac stress with dc offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, are measured to verify the impact of gate-oxide reliability on circuit performances of the operational amplifier. The gate-oxide reliability in the operational amplifier can be improved by the stacked configuration under small-signal input and output application. The impact of soft and hard gate-oxide breakdowns on operational amplifiers with two-stage and folded-cascode structures has been analyzed and discussed. The hard breakdown has more serious impact on the operational amplifier.

  • A unified gate oxide reliability model

    Existing literature indicates that there are two major mechanisms involved in the time dependent dielectric breakdown (TDDB) of silicon dioxide, and each mechanism dominates under different stress conditions. We suggest that the thermochemical (linear E) model and the hole-induced (1/E) model can be unified in one model. Based on the unified model, a wide range of TDDB data from different sources were examined and shown to behave consistently. Temperature and stress field dependencies are treated together in the model so that the lifetime is a single-valued function of temperature and field. The criterion for screen/ramp breakdown test is also discussed with the model. Furthermore, the unified model accounts for the effect of gross defects, which limit the oxide reliability in real ICs. The model is be used to predict the 10-year lifetime breakdown field or acceptable oxide thickness for a given voltage, and results suggest that further refinements for thin oxide (<5 nm) are necessary.

  • Effect of electronic corrections on the thickness dependence of thin oxide reliability

    The thickness dependence of constant voltage lifetime tests for thin oxides in the range of 50-125 /spl Aring/ show an apparent factor of 100 enhancement in the lifetime of 50 /spl Aring/ oxides relative to the 125 /spl Aring/ oxides at a fixed electric field. However, when corrections are made for the distribution of electrons at the silicon interface, including depletion in the silicon and quantum-mechanical screening effects, then this apparent enhancement is reduced and all oxides have similar lifetimes at a fixed field. This rescaling of oxide reliability demonstrates the importance of accurate determination of the electric field and oxide voltage in thin oxides, and that oxide reliability is not significantly affected by thickness down to 50 /spl Aring/, depending only on field. We compare different techniques for determining the effective thickness using current-voltage or capacitance- voltage curves. We show that accurate estimates of the electric field can be obtained from integration of the capacitance-voltage relation of the capacitor. When electric fields are calculated using C-V curves, a consistent set of extrapolation parameters can be obtained for all thicknesses.

  • Gate current and oxide reliability in p/sup +/ poly MOS capacitors with poly-Si and poly-Ge/sub 0.3/Si/sub 0.7/ gate material

    Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p/sup +/ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge/sub 0.3/Si/sub 0.7/) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, /spl phi//sub B/, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q/sub bd/) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.

  • Improvement of gate oxide reliability for tantalum-gate MOS devices using xenon plasma sputtering technology

    The effects of ion species in the sputtering deposition process on gate oxide reliability have been experimentally investigated. The use of xenon (Xe) plasma instead of argon (Ar) plasma in tantalum (Ta) film sputtering deposition for gate electrode formation makes it possible to improve the gate oxide reliability. The Xe plasma process exhibits 1.5 times higher breakdown field and five times higher 50%-charge-to-breakdown (Q/sub BD/). In the Ta sputtering deposition process on gate oxide, the physical bombardment of energetic inert-gas ion causes the generation of hole trap sites in gate oxide, resulting in the lower gate oxide reliability. A simplified model providing a better understanding of the empirical relation between the gate oxide damage and the inert-gas ion bombardment energy in the gate-Ta sputtering deposition process is also presented.

  • Modeling kinetics of gate oxide reliability using stretched exponents

    In this work, we propose a novel approach to modeling the kinetics of gate oxide reliability, using the stretched-exponential form. We show how the dispersive nature of characteristic times pertaining to kinetic transitions during oxide degradation, are very well captured by stretched-exponential functions. We demonstrate their use in common oxide reliability concerns such as hot-carrier injection and negative bias temperature instability. The use of the stretched exponents to model oxide reliability is demonstrated with two real examples.

  • F contamination effects on intrinsic and extrinsic gate oxide reliability

    The subject of this work is the study of the effect of fluorine contaminants on the intrinsic and extrinsic gate oxide reliability. After a brief introduction in which the author explains the known effects of fluorine contaminants on the oxide quality, the the test structures used in this work to separate the effect of fluorine contaminants are described. The author then presents some typical TDDB distributions showing the effects of fluorine contaminants and reports also a study of the TDDB dependence on the tested areas to verify if clustering of defects are present at such high fluorine concentrations. The author explains how he statistically treated the experimental results. He considered bimodal distributions separated in an intrinsic and an extrinsic part, showing in detail the effects of fluorine on the intrinsic and extrinsic failure mode. The author also presents some data on charge trapping to explain the above results and finally draws some conclusions.



Standards related to Oxide Reliability

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