IEEE Organizations related to Semiconductor Device Reliability

Back to Top

No organizations are currently tagged "Semiconductor Device Reliability"



Conferences related to Semiconductor Device Reliability

Back to Top

No conferences are currently tagged "Semiconductor Device Reliability"


Periodicals related to Semiconductor Device Reliability

Back to Top

No periodicals are currently tagged "Semiconductor Device Reliability"


Most published Xplore authors for Semiconductor Device Reliability

Back to Top

Xplore Articles related to Semiconductor Device Reliability

Back to Top

Assembly Level Reliability

International Report on Wafer Level Reliability Workshop, 1992

None


A new "mixed-mode" reliability degradation mechanism in advanced Si and SiGe bipolar transistors

IEEE Transactions on Electron Devices, 2002

A new mixed-mode base current degradation mechanism is identified in bipolar transistors for the first time, which, at room temperature, induces a large I/sub B/ leakage current only after simultaneous application of both high J/sub C/ and high V/sub CB/. This new mechanism differs fundamentally from well-known I/sub B/ degradation mechanisms such as the reverse EB voltage stress, high forward ...


Consistency Of Similarly Designed Wafer Level Reliability test Structures Produced In Multiple Fabrication Areas

International Report on Wafer Level Reliability Workshop, 1992

None


Practical application of a wafer level reliability qualification

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS), 1994

Deficiencies in the traditional approach to ensuring product reliability (e.g. package level testing) were first noted way back in the early 1970's. However, it was not until the late 1980's to early 1990's that WLRC was seriously considered and began to be implemented across the industry. This new approach for achieving greater levels of reliability required a fundamental change from ...


"Static Or Dynamic", The Selection Process For A Memory System

COMPCON '77, 1977

None


More Xplore Articles

Educational Resources on Semiconductor Device Reliability

Back to Top

IEEE-USA E-Books

  • Assembly Level Reliability

    None

  • A new "mixed-mode" reliability degradation mechanism in advanced Si and SiGe bipolar transistors

    A new mixed-mode base current degradation mechanism is identified in bipolar transistors for the first time, which, at room temperature, induces a large I/sub B/ leakage current only after simultaneous application of both high J/sub C/ and high V/sub CB/. This new mechanism differs fundamentally from well-known I/sub B/ degradation mechanisms such as the reverse EB voltage stress, high forward current stress and damage due to ionizing radiation. Extensive measurements and two-dimensional (2-D) simulations have been used to help understand the device physics associated with this new degradation mechanism.

  • Consistency Of Similarly Designed Wafer Level Reliability test Structures Produced In Multiple Fabrication Areas

    None

  • Practical application of a wafer level reliability qualification

    Deficiencies in the traditional approach to ensuring product reliability (e.g. package level testing) were first noted way back in the early 1970's. However, it was not until the late 1980's to early 1990's that WLRC was seriously considered and began to be implemented across the industry. This new approach for achieving greater levels of reliability required a fundamental change from the mind set of reliability verification on finished products (screening the outputs) to comprehending and controlling the various factors that determine reliability (controlling the inputs). This mind set is known as "building-in" or "designing-in" reliability and envisions a total reliability assurance and improvement strategy that is executed at all stages of semiconductor manufacturing. To meet the challenge of continuous improvement, it is now a corporate policy that a WLRC program be required at all R&D; and production facilities with the intention of determining and eliminating all faults at their source of origin. Emphasis is placed on the use of wafer level reliability testing for introducing and qualifying new semiconductor technology and controlling production once technology has been transferred to the wafer fab. The description, philosophy and issues of integrating the WLRC program into a manufacturing environment have been described previously. Here a practical application is presented. As an example, the development, execution and results of a WLR qualification and production control plan for an advanced, submicron, triple-level metal CMOS process is provided.

  • "Static Or Dynamic", The Selection Process For A Memory System

    None

  • On comparing functional fault coverage and defect coverage for memory testing

    The manufacturing of high-quality and reliable semiconductor memories is very important. Many memory testing algorithms have been proposed to improve the quality of semiconductor memories by screening out different memory functional faults. However, the relationships between memory function fault types and the types of defects which cause the functional faults are not well understood. Therefore, the effectiveness of memory testing algorithms based on the functional fault models cannot be realistically determined. This paper evaluates the effectiveness of the memory testing algorithms based on the defect coverage by comparing the defect coverage of known memory testing algorithms and the functional fault coverage of the same testing algorithms using the same defect statistics. The experimental results show that the differences among the defect coverage of the 11 memory testing algorithms other than checkerboard and sliding diagonal tests were not significant as previously believed using memory functional fault coverage as the coverage metric.

  • Failure Reporting, Analysis And Corrective Action System In The US Semiconductor Manufacturing Equipment Industry: A Continuous Improvement Process

    None

  • 400 MHz-A Challenge for the Hybrid Amplifier

    Throughout its history, the CATV industry has seen an increasing demand for extended system bandwidth. The latest move raises the upper frequency limit to 400 MHz, thus providing space for 52 channels.

  • Studies on the Possibilities of In-Line Die Attach Characterization of Semiconductor Devices

    The qualification of the die attach of semiconductor devices is a very important element of predicting the reliability of the package, as the temperature of the chip is strongly affected by the quality of the die attach. This paper describes our latest findings on die attach quality testing of semiconductor devices using short term thermal transient measurements. Using estimates from simulations as well as from measured structure functions of power transistors with known die attach quality we found that cca the first 100ms section of thermal transients is sufficient to draw conclusion on die attach quality. In case of in-line application of the short term thermal transient measurements however, there are different difficulties such as lack of time for K-factor calibration of the individual devices under test. In this paper we describe certain techniques which have been validated on large number of power LEDs with the aim of application in in line testing of die attach quality.

  • Finite element simulation of the temperature cycling tests

    Temperature cycling tests are commonly used in the semiconductor industry to determine the number of cycles to failure and to predict reliability of the solder joints in the surface mount technology packages. In this paper, the thermomechanical fatigue of Pb40/Sn60 solder joint in a leadless ceramic chip carrier package is studied and temperature cycling test is simulated by using a finite element procedure with the disturbed state concept (DSC) constitutive models. The progress of disturbance (damage) and the energy dissipated in the solder joint during thermal cycling are predicted. It is shown that the disturbance criterion used follows a similar path as the energy dissipation in the system. Moreover, the comparisons between the test data and the finite element analysis show that a finite element procedure using the DSC material models can be instrumental in reliability analysis and to predict the number of cycles to failure of a solder joint. Furthermore, the analysis gives a good picture of the progress of the failure mechanism and the disturbance in the solder joint.



Standards related to Semiconductor Device Reliability

Back to Top

No standards are currently tagged "Semiconductor Device Reliability"


Jobs related to Semiconductor Device Reliability

Back to Top