What Is IEEE Transactions on Very Large Scale Integration - VLSI?

IEEE Transactions on Very Large Scale Integration Systems (T-VLSI) is a peer-reviewed monthly journal that publishes research on the design and realization of microelectronic systems using VLSI and ULSI (ultra-large-scale integration) technologies. The journal is co-sponsored by the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society, reflecting the interdisciplinary nature of VLSI design, which requires collaboration across system architecture, logic and circuit design, silicon fabrication, packaging, and testing. It has been published since 1993 and serves as a primary archival venue for the community responsible for the silicon devices underlying modern computing and communications.

Very large scale integration refers to the process of integrating hundreds of thousands to billions of transistors onto a single semiconductor chip. VLSI design transformed computing during the 1970s and 1980s as design automation tools made it practical to build ever more complex circuits, and the journal was founded to provide a single venue that could hold research spanning the full abstraction hierarchy, from process technology up to system-level architecture.

Design Methodology and Abstraction Levels

T-VLSI covers design work at all abstraction levels: system, register-transfer, logic, circuit, transistor, and process. Research at the system and register-transfer levels includes hardware description language synthesis, high-level optimization, and hardware-software co-design. At the circuit and transistor levels, papers address analog and mixed-signal circuits, power delivery networks, clock distribution, and parasitic extraction. The journal's scope statement, as maintained through the IEEE Circuits and Systems Society's T-VLSI program, specifically requires that analog and mixed-signal submissions be consistent with the VLSI/ULSI implementation emphasis rather than analog circuit theory in isolation.

Emerging Architectures and Technologies

A substantial portion of T-VLSI's content addresses architectures that push against the limits of conventional CMOS scaling. These include reconfigurable computing systems built around FPGAs, neural network hardware accelerators, application-specific integrated circuits (ASICs) for signal processing and cryptography, and system-on-chip (SoC) designs that integrate processor cores, memory, and I/O on a single die. The journal also publishes research on three-dimensional integrated circuits, chiplet-based heterogeneous integration, and emerging memory technologies such as resistive RAM and phase-change memory. Complete scope and submission guidelines are maintained at the T-VLSI scope and call for papers page.

Testing, Verification, and Reliability

Testing and verification form a persistent theme throughout T-VLSI, as the complexity of modern integrated circuits makes comprehensive validation both critical and computationally challenging. Papers in this area cover design-for-testability (DFT) techniques, built-in self-test (BIST) circuits, fault modeling, scan chain insertion, and the increasingly important problem of testing three-dimensional stacked dies. Reliability research addresses electromigration, gate oxide wear-out, soft errors caused by cosmic ray strikes, and the statistical variability introduced by transistor scaling below ten nanometers. Work from standards bodies such as IEEE Std 1149.1 (JTAG), which defines boundary-scan testing architecture, frequently provides the normative baseline against which new testing methodologies are evaluated.

Applications

IEEE Transactions on Very Large Scale Integration Systems publishes research with applications in a wide range of disciplines, including:

• Microprocessors and graphics processing units for high-performance computing
• Application-specific processors for AI inference and signal processing
• System-on-chip designs for mobile and embedded computing
• Memory architectures for storage and caching
• Mixed-signal integrated circuits for sensor interfaces and wireless transceivers