What Are Three-dimensional Integrated Circuits?

Three-dimensional integrated circuits (3D ICs) are semiconductor devices constructed by stacking two or more silicon dies or wafers vertically and connecting them with short electrical interconnects that pass through or between the layers. The approach addresses a fundamental constraint of conventional planar IC design: as transistor density on a single die approaches physical limits, and as long horizontal interconnects increasingly dominate propagation delay and power consumption, vertical integration provides a path to increased performance and functional density without requiring further lithography scaling. Three-dimensional ICs are a product of advanced IC design practice and semiconductor packaging technology, combining expertise in circuit design, materials science, and process engineering.

The concept of stacking dies was explored experimentally from the 1980s onward, but the enabling infrastructure, particularly through-silicon via fabrication and precision wafer bonding, reached manufacturing maturity in the early 2000s. By the 2010s, 3D NAND flash memory had become the first high-volume commercial application, with stacks of 100 or more layers in production by the mid-2020s.

Through-Silicon Via Technology

The dominant interconnect technology for 3D ICs is the through-silicon via (TSV): a vertical conductive channel, typically filled with copper or tungsten, that passes completely through a thinned silicon die to make electrical contact with the die above or below it. TSVs are formed by etching high-aspect-ratio holes into the silicon using deep reactive-ion etching, lining them with a dielectric barrier and adhesion layer, and filling them with electrodeposited metal. Via dimensions range from a few micrometers in diameter for high-density logic applications to tens of micrometers for power and signal distribution. The shortened path length compared to off-chip wire bonds reduces propagation delay and energy consumption per bit transferred. An IEEE Xplore study on 3D chip-stacking with through-silicon vias documents the process integration challenges and electrical performance results from early IBM research on TSV interconnects.

IC Design Considerations for 3D Integration

Designing a circuit to be partitioned and stacked across multiple dies introduces challenges that do not arise in conventional single-die IC design. The physical design tool chain must account for inter-die timing closure, where signals crossing a TSV face a different parasite profile than on-chip wires. Power delivery to upper dies must pass through the lower layers, requiring careful analysis of IR drop through the TSV power grid. Heat generated in an upper die cannot dissipate through the back side of the wafer as easily as in a conventional package, so thermal analysis of the stack must be performed during floor planning. Synopsys's 3D-IC design reference describes the EDA tool flows that handle cross-die timing, power, and thermal co-optimization, which are now standard parts of the IC design flow for advanced packaging.

Stacking Configurations and Bonding Methods

Three-dimensional ICs are assembled through several bonding approaches. Die-to-die bonding places known-good die on a carrier wafer or substrate after individual testing, maximizing yield by avoiding the assembly of defective components. Wafer-to-wafer bonding bonds two full wafers before dicing, which simplifies alignment but requires both wafers to have high yield for the bonded assembly to be economical. Hybrid bonding, which forms direct copper-to-copper and oxide-to-oxide bonds without solder, achieves sub-micron pitch and is used in advanced image sensor and logic-on-memory stacking. Imec's 3D integration research program documents the bonding technology roadmap and the pitch scaling trajectory for commercial applications.

Applications

Three-dimensional integrated circuits have applications in a range of fields, including:

• High-bandwidth memory (HBM) stacks for graphics processors and AI accelerators
• 3D NAND flash memory with 100-plus active layers for solid-state storage
• Logic-on-memory integration for near-memory computing and data center workloads
• Mobile SoC packaging combining processor, DRAM, and radio dies
• Image sensors with stacked processing circuits directly beneath the pixel array