FinFETs

What Are FinFETs?

FinFETs are a class of non-planar metal-oxide-semiconductor field-effect transistors in which the channel is formed in a thin vertical fin of semiconductor material that projects above the substrate surface. Unlike conventional planar MOSFETs, where the gate electrode sits on only one side of the channel, the FinFET gate wraps around three sides of the fin, giving the device superior electrostatic control over the channel. This architecture suppresses the short-channel effects, such as threshold voltage roll-off and drain-induced barrier lowering, that had begun to degrade planar transistor performance as feature sizes shrank below 25 nm.

The FinFET concept was first demonstrated in 1989 by researchers at the Hitachi Central Research Laboratory in Japan, who called the device a depleted lean-channel transistor (DELTA). The architecture was further developed and named at the University of California, Berkeley, in work led by Chenming Hu, who received the IEEE Medal of Honor in 2020 for extending Moore's Law by taking the transistor into three dimensions.

Device Structure and Electrostatics

The defining feature of a FinFET is the narrow semiconductor fin, typically 5 to 15 nm wide in production devices, whose height-to-width ratio determines the effective gate coupling to the channel. The gate dielectric wraps the fin on its top and two sidewalls, creating the multi-gate geometry that gives the transistor its name. Charge carriers flow through the fin from source to drain along the fin's length, with the surrounding gate controlling the barrier height. The reduced fin width limits the depletion length, preventing the drain's electric field from penetrating far into the channel region and suppressing the leakage current that plagued planar devices at equivalent gate lengths. A comprehensive review of FinFET technology published in MDPI Micromachines covers the structural parameters and electrostatic tradeoffs that guide fin geometry selection in modern process nodes.

Fabrication and Process Technology

Manufacturing FinFETs requires precise control of fin patterning, which is typically performed with extreme ultraviolet (EUV) lithography or multi-patterning techniques at the 7 nm node and below. Fin pitch, fin height uniformity, and sidewall profile directly affect threshold voltage, drive current, and variability across a wafer. The integration of high-k dielectrics and metal gate stacks, pioneered for planar transistors at the 45 nm node, carries over directly to FinFET processes. Intel commercialized the first volume FinFET products in 2012 with its 22 nm process node, and the device became the standard architecture at 14 nm, 10 nm, and 7 nm nodes across leading foundries. IEEE Xplore publications on FinFET technology and circuit design challenges detail the process integration issues that arose as the technology scaled to production volumes.

Performance Characteristics and Limitations

FinFETs deliver substantially lower leakage current at equivalent drive current compared with planar transistors, enabling products that operate at lower supply voltages and consume less power for the same computational throughput. The quantized nature of fin widths, however, limits the designer's ability to tune transistor drive strength continuously; width must be adjusted in discrete fin increments. Variability from line-edge roughness in patterned fins introduces threshold voltage spread that circuit designers must accommodate with guard-band margins. As process nodes continued below 5 nm, the gate-all-around (GAA) nanosheet transistor architecture emerged as the successor to FinFETs, extending the multi-gate principle by fully enclosing the channel on all four sides. IEEE Spectrum's coverage of FinFET developments has tracked the competitive dynamics among Intel, TSMC, and Samsung as each foundry refined its FinFET and GAA process generations.

Applications

FinFETs have applications in a wide range of domains, including: