What Is a Field Programmable Gate Array (FPGA)?

A field programmable gate array (FPGA) is a semiconductor device containing an array of configurable logic blocks, programmable interconnects, and dedicated hardware resources whose function is determined by configuration data loaded after manufacture rather than by the physical layout of the chip. The term "field programmable" reflects the fact that the device can be configured and reconfigured outside the factory, in the field, without hardware modification. Xilinx introduced the first commercial FPGA in 1985, and the technology has since grown into a major product category used across telecommunications, defense, data centers, and embedded systems.

FPGAs occupy a position between fixed-function application-specific integrated circuits (ASICs) and general-purpose processors. An ASIC delivers the best possible performance per watt for a single function, but requires months of design time and substantial mask costs. A processor executes software flexibly but serially. An FPGA implements many logic operations in parallel and can be updated by loading a new configuration bitstream, combining hardware parallelism with design flexibility. Modern FPGAs from Intel (formerly Altera) and AMD (formerly Xilinx) integrate hundreds of thousands to millions of logic elements alongside dedicated DSP blocks, high-bandwidth memory interfaces, and embedded processor cores.

Logic Fabric and Reconfigurability

The fundamental building block of an FPGA's programmable logic is the configurable logic block (CLB), which contains lookup tables (LUTs) and flip-flops. A LUT is a small memory whose output depends on its input address, allowing it to implement any Boolean function up to the number of inputs it has; most modern FPGAs use 4-input or 6-input LUTs. Flip-flops store state, enabling sequential logic. The CLBs connect through a programmable routing network of wire segments and switching matrices. Because both the logic function of each LUT and the routing connections are stored in static RAM cells, the entire design can be changed simply by loading a new configuration file. This reconfigurability enables use cases such as hardware accelerators that adapt to different workloads, in-field firmware updates, and hardware prototyping before ASIC tape-out. The architecture overview for Intel FPGAs is documented in the Intel FPGA Developer Guide.

Embedded Memory Architectures

Modern FPGAs incorporate substantial on-chip memory resources, a design choice that reflects the memory-bandwidth requirements of high-throughput processing pipelines. Block RAM (BRAM) tiles are distributed throughout the logic fabric, typically in a grid that ensures any logic region has a nearby memory resource. Each BRAM can be configured as single-port or dual-port memory and serves as a line buffer, coefficient storage for DSP filters, FIFO queues, or lookup tables too large for LUT-based implementation. FPGA architectures also include ultra-RAM (URAM) in larger devices, offering higher density than BRAM at the cost of fewer access ports. At the interface to the outside world, hard memory controllers for DDR4 and DDR5 SDRAM, HBM (high-bandwidth memory), and various serial memory standards are embedded as fixed-function blocks adjacent to the I/O periphery. These embedded memory architectures determine, to a large extent, the maximum data throughput an FPGA design can sustain. IBM's overview of FPGA technology addresses the interplay between logic, memory, and compute resources in contemporary devices at IBM Think Topics.

Design Flow and Tools

FPGA designs are typically described in a hardware description language such as VHDL or Verilog, then synthesized and placed-and-routed using vendor-supplied toolchains (Xilinx Vivado, Intel Quartus). High-level synthesis (HLS) tools allow C or C++ descriptions to be compiled into RTL, lowering the barrier for software engineers implementing hardware accelerators. After place-and-route, the toolchain generates a configuration bitstream that is downloaded to the FPGA through a JTAG interface or loaded from flash memory at power-up. Partial reconfiguration is a feature of high-end FPGAs that allows a portion of the device to be reconfigured while the remainder continues operating, enabling dynamic hardware updates without system downtime. National Instruments provides a practical overview of FPGA fundamentals and design methodology covering the LUT-to-bitstream flow.

Applications

Field programmable gate arrays have applications in a wide range of disciplines, including:

• Network packet processing and deep packet inspection at line rate
• Machine learning inference acceleration in data centers
• Software-defined radio signal processing
• Real-time image and video processing pipelines
• ASIC prototyping and pre-silicon hardware validation
• High-frequency trading infrastructure requiring deterministic latency