What Are Asynchronous Circuits?

Asynchronous circuits are digital logic circuits that operate without a global clock signal, instead using local handshaking signals between modules to coordinate computation and data transfer. In contrast to synchronous circuits, which advance from state to state on a clock edge distributed to all flip-flops simultaneously, asynchronous circuits start processing when input data arrives and signal completion when output data is ready. This event-driven model eliminates the need for a circuit-wide timing reference, removing the global clock distribution network that consumes substantial power and introduces design complexity in large synchronous integrated circuits. Asynchronous circuit design draws on formal specification methods, concurrency theory, and IC fabrication knowledge.

Design Principles and Handshaking

The coordination mechanism that replaces the clock in asynchronous circuits is the handshake protocol: a request-acknowledge exchange between a sender and a receiver that confirms data availability and acceptance before advancing. Two main handshake families are in common use. The four-phase (return-to-zero) protocol uses a request transition to signal data validity, an acknowledge transition to confirm receipt, and then both signals return to zero before the next communication. The two-phase (transition-signaling) protocol encodes each communication as a wire transition in either direction, halving the number of signal events per handshake and improving throughput on low-capacitance links. An accessible treatment of both protocols and their trade-offs appears in the Portland State Asynchronous Research Center's introduction to asynchronous circuit design. The choice of protocol propagates through the entire design methodology, influencing cell libraries, synthesis tools, and verification flows.

Delay Models and Circuit Families

Asynchronous circuits are classified by the assumptions they make about component and wire delays. Speed-independent (SI) circuits assume that all gates have finite but unbounded delays while wires are ideal; quasi-delay-insensitive (QDI) circuits additionally allow wires to have unbounded delays, making QDI correctness independent of technology scaling. Bundled-data circuits relax these constraints by requiring that data path delays are bounded by matched delay elements, permitting the use of standard-cell implementations. QDI circuits, because they make the fewest timing assumptions, are the most resistant to process variation and voltage scaling, but they require a data encoding that conveys completion information directly, typically using dual-rail or multi-rail codes such as 1-of-N encoding. Synchronous designers moving to asynchronous flows encounter distinct synthesis and timing verification challenges: there is no static timing analysis in the synchronous sense, and formal verification of the handshake protocol correctness replaces setup/hold time checks.

Power and Performance Characteristics

Asynchronous circuits dissipate dynamic power only when they perform computation: a module that is idle does not switch and therefore draws no dynamic power. This activity-dependent power profile contrasts with synchronous circuits, where clock buffers and flip-flops switch on every clock edge regardless of whether new data has arrived. The Galois article on asynchronous design documents how QDI circuits naturally support power gating without timing analysis overhead, since the handshake protocol itself signals readiness. Asynchronous circuits also tolerate wider supply voltage variation without functional failure, because slower switching at reduced voltage simply increases handshake latency without violating any timing constraint. These properties make them attractive for applications where power varies widely over time or where supply voltage is not tightly regulated. Research on low-power asynchronous design has shown that significant dynamic power savings are achievable compared to clocked equivalents in data-sparse workloads.

Applications

Asynchronous circuits have applications in a range of fields and design contexts, including:

• Ultra-low-power wearable and implantable medical devices
• Secure cryptographic hardware resistant to clock-based side-channel analysis
• Self-timed memory interfaces and first-in, first-out (FIFO) buffers between clock domains
• High-performance arithmetic units in processors where latency varies with input data
• Radiation-hardened electronics for space and defense environments