What Are 3D Devices?

3D devices are electronic components and integrated circuits whose active elements are organized in three spatial dimensions rather than confined to a single plane on a semiconductor substrate. The category encompasses three-dimensional transistor architectures, vertically stacked memory arrays, and multi-tier integrated circuits that extend device density and performance beyond what planar scaling can achieve. The transition to 3D structures in semiconductor engineering was driven by the progressive slowdown of conventional lateral scaling as defined by Moore's Law: by approximately 2010, further reductions in planar gate length yielded diminishing improvements in performance and power efficiency, motivating the industry to exploit the vertical dimension. Device reliability under the thermal and mechanical stresses introduced by vertical stacking has become a central engineering consideration alongside performance metrics.

3D devices draw from semiconductor physics, materials science, process integration, and electronic design automation. Major logic and memory manufacturers, including Intel, Samsung, SK Hynix, and TSMC, have committed substantial fabrication resources to 3D device development.

3D Transistor Architectures

The FinFET, introduced commercially by Intel in its 22 nm process node in 2011, was the first widely deployed 3D transistor. It wraps the gate conductor around a vertical silicon fin on three sides, improving electrostatic control of the channel compared to a planar gate structure. Gate-all-around (GAA) nanosheet and nanowire transistors, which surround the channel on all four sides, extend this principle further and are entering production at leading-edge nodes below 3 nm. A more aggressive approach stacks complementary transistors vertically: the NMOS device is fabricated on top of the PMOS device over the same footprint, approximately halving the cell area compared to a conventional side-by-side layout. The IEEE Spectrum article on 3D-stacked CMOS and Moore's Law extension describes the fabrication and circuit implications of stacked complementary transistors in detail.

3D IC Design and Integration

Three-dimensional integrated circuits combine multiple die or transistor layers into a single package, connected by vertical interconnects. Through-silicon vias (TSVs), micrometer-scale copper-filled holes etched through the silicon substrate, are the established interconnect technology for die-to-die vertical connections. Hybrid bonding, which directly bonds copper pads on facing die surfaces without solder, achieves finer pitch and lower resistance than TSV-based approaches and is now used in high-bandwidth memory (HBM) stacks and advanced image sensor packages. Design for 3D ICs requires thermal analysis across the stack, because heat generated in buried layers must conduct through multiple material interfaces to reach the heat sink. The Cadence explanation of 3D-IC technology and design methodology covers the design automation tools and physical verification requirements for 3D integration.

Emerging Memory Devices

Three-dimensional organization has transformed non-volatile memory design. 3D NAND flash, commercialized by Samsung in 2013 with its V-NAND architecture, stacks charge-storage cells vertically through tens to over a hundred layers, achieving areal bit densities unattainable with planar NAND at comparable lithographic dimensions. Emerging non-volatile memory technologies including 3D XPoint (now Optane), resistive RAM (ReRAM), and phase-change memory (PCM) are also implemented in vertical array structures, exploiting crossbar geometries with one selector and one storage element per intersection. These technologies target the gap between DRAM latency and NAND flash capacity. The MIT News report on 3D chip stacking for faster and more energy-efficient electronics highlights recent research combining logic and memory layers in a single 3D stack to reduce data movement energy.

Applications

3D devices have applications in a range of fields, including:

• High-bandwidth memory (HBM) stacks for GPU and AI accelerator systems
• Smartphone and mobile devices requiring dense storage in constrained form factors
• Data center storage with 3D NAND SSDs at high bit density
• Aerospace and defense electronics requiring radiation-tolerant compact assemblies
• Neuromorphic and in-memory computing research platforms