Wafer bonding

View this topic in
Wafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS), microelectronics and optoelectronics, ensuring a mechanically stable and hermetically sealed encapsulation. (Wikipedia.org)






Conferences related to Wafer bonding

Back to Top

2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation


2020 Optical Fiber Communications Conference and Exhibition (OFC)

The Optical Fiber Communication Conference and Exhibition (OFC) is the largest global conference and exhibition for optical communications and networking professionals. For over 40 years, OFC has drawn attendees from all corners of the globe to meet and greet, teach and learn, make connections and move business forward.OFC attracts the biggest names in the field, offers key networking and partnering opportunities, and provides insights and inspiration on the major trends and technology advances affecting the industry. From technical presentations to the latest market trends and predictions, OFC is a one-stop-shop.


More Conferences

Periodicals related to Wafer bonding

Back to Top

Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Design & Test of Computers, IEEE

IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


More Periodicals

Most published Xplore authors for Wafer bonding

Back to Top

Xplore Articles related to Wafer bonding

Back to Top

Building In Reliability For Packaging And Assembly

International Report on Wafer Level Reliability Workshop, 1992

None


Hybrid silicon wafer-scale packaging technology

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1986

Procedures developed for mounting ICs in holes in a silicon wafer and inter- connecting them, via two-level metalization, will be presented. The performance of the interconnections at high speeds will be compared with traditional hybrid assemblies.


A high-speed, low-power 3D-SRAM architecture

2008 IEEE Custom Integrated Circuits Conference, 2008

This paper presents a novel 3D-SRAM architecture that can be used to extend the scaling of SRAM. This architecture significantly reduces the bit-line capacitance, achieves 3.4 times reduction in active power consumption and 1.8 times reduction in access time. In this architecture, local bit-lines are vertical and connect through select transistors to the global bit-lines routed on the bottom level. ...


A 150-V multiple up-drain VDMOS, CMOS, and bipolar process in 'direct-bonded' silicon on insulator on silicon

IEEE Electron Device Letters, 1992

Silicon on insulator on silicon (SOIS) has been produced with silicon direct bonding (SDB). Within a silicon film of 15- mu m thickness, islands with ubiquitous oxide isolation have been formed for the simultaneous integration of 150-V power VDMOS transistors, CMOS circuits in a channelless sea-of-gates array with 2- mu m gates, and bipolar transistors. The up-drain VDMOS transistors with ...


Back gated CMOS on SOIAS for dynamic threshold voltage control

Proceedings of International Electron Devices Meeting, 1995

Simultaneous reduction of supply and threshold voltages for low power design without suffering performance losses will eventually reach the limit of diminishing returns as static power dissipation becomes a significant portion of the total power equation. In order to meet the opposing requirements of high performance and low power, a dynamic threshold voltage control scheme is needed. A novel SOI ...


More Xplore Articles

Educational Resources on Wafer bonding

Back to Top

IEEE-USA E-Books

  • Building In Reliability For Packaging And Assembly

    None

  • Hybrid silicon wafer-scale packaging technology

    Procedures developed for mounting ICs in holes in a silicon wafer and inter- connecting them, via two-level metalization, will be presented. The performance of the interconnections at high speeds will be compared with traditional hybrid assemblies.

  • A high-speed, low-power 3D-SRAM architecture

    This paper presents a novel 3D-SRAM architecture that can be used to extend the scaling of SRAM. This architecture significantly reduces the bit-line capacitance, achieves 3.4 times reduction in active power consumption and 1.8 times reduction in access time. In this architecture, local bit-lines are vertical and connect through select transistors to the global bit-lines routed on the bottom level. A proof-of-concept 32Kb sub-array emulating the critical path of the 3D-SRAM has demonstrated about 5 times improvement in power-delay over conventional 2D-SRAM.

  • A 150-V multiple up-drain VDMOS, CMOS, and bipolar process in 'direct-bonded' silicon on insulator on silicon

    Silicon on insulator on silicon (SOIS) has been produced with silicon direct bonding (SDB). Within a silicon film of 15- mu m thickness, islands with ubiquitous oxide isolation have been formed for the simultaneous integration of 150-V power VDMOS transistors, CMOS circuits in a channelless sea-of-gates array with 2- mu m gates, and bipolar transistors. The up-drain VDMOS transistors with 2- Omega -mm/sup 2/ specific on-resistance allow multiple isolated outputs, so high-voltage push-pull drivers can be fabricated in a single chip. The bipolar transistors are comparable to those of a 60-V standard process with vertical n-p-n and lateral p-n-p current gains of 80.<<ETX>>

  • Back gated CMOS on SOIAS for dynamic threshold voltage control

    Simultaneous reduction of supply and threshold voltages for low power design without suffering performance losses will eventually reach the limit of diminishing returns as static power dissipation becomes a significant portion of the total power equation. In order to meet the opposing requirements of high performance and low power, a dynamic threshold voltage control scheme is needed. A novel SOI technology was developed whereby a back-gate was used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process.

  • Micro-Corrosion of Al-Cu Bonding Pads

    Aluminum metallization films with copper additions are found to exhibit highly localized pitting in the presence of moisture. Galvanic action of aluminum surrounding Al<inf>2</inf>Cu theta phase particles causes localized aluminum corrosion. The thin layer of aluminum hydroxide corrosion product on the bonding pad creates an effective barrier to high-quality wire bonding.

  • Photo-pumped operation of InGaAsP vertical-cavity lasers on Si fabricated by wafer bonding

    Long-wavelength vertical cavity lasers have been successfully fabricated on Si substrates using a wafer bonding technique. InGaAs/InGaAsP multi-quantum well active layers with 40.5-pair InGaAsP/InP stacked mirrors have been directly bonded on 3.5-pair Al/sub 2/O/sub 3//a-Si mirrors deposited on Si substrates. The sample has been optically pumped at room temperature and lasing operation at 1.58-/spl mu/m has been achieved.

  • Novel 3-D structures [ICs]

    Summary form only given. Interconnect delays are increasingly dominating IC performance due to increased chip size and reductions in minimum feature size. Despite new materials like Cu with low-k dielectrics, interconnect delay is expected to be substantial below the 130 nm technology node, severely limiting chip performance. The need therefore exists for alternative technologies to overcome this problem. One such promising technique is 3D ICs with multiple active Si layers. In a 3D structure, a large number of information signal paths could be transferred from horizontal to vertical interconnects. 3D device integration in multiple Si layers obtainable via technologies like crystallization of amorphous Si and wafer bonding can potentially reduce chip area by increasing transistor packing density and reducing wiring requirements for wire-pitch limited ICs. Recently, we have estimated chip area for 3D ICs and demonstrated significant reductions in interconnect delay for a 0.18 /spl mu/m technology chip with 8 million gates (Souri et al., 1999). In this work, we generalize this analysis using NTRS technology projections down to the 50 nm node. The performance analysis incorporates the effects of increasing the number of active layers, moving repeaters from the substrate to upper active layers and optimizing wiring networks. Interconnect delay as a function of technology is calculated using data projected by the NTRS for 2D ICs. Also shown are delays for 3D ICs with 2 active layers, where wire pitches are increased to match the 2D IC areas, calculated using the 3D chip area estimation model. Interconnect delay is reduced by 64%.

  • Structure Design and Fabrication of an Area-changed Bulk Micromachined Capacitive Accelerometer

    In this paper, a lateral capacitive MEMS accelerometer for low-g applications was designed and fabricated. The accelerometer is chosen to be based on an area-changed detection scheme. Area-changed accelerometers can provide alternatives in designing high sensitivity and low mechanical noise floor sensors as it is capable of providing a large proof mass. Based on the calculation of sensitivity and basic resonance frequency, three kinds of accelerometers were designed and optimized. Bulk silicon is chosen as the proof mass material and a three-mask micromachining technology was adopted to fabricate the active structures of the accelerometer. Deep RIE and wafer bonding techniques are utilized as it offers solutions in fabricating the thick proof mass and high aspect ratio sensing element structures with small sensing gaps to achieve high sensitivity and low noise performance.

  • The transport and deformation of blood cells in micro-channel

    The transport and deformability of erythrocyte (RBC) and leukocyte (WBC) play great roles in both microcirculation in vivo and blood cell diagnosis. This paper used the microfabricated chips to study the transport and deformation of blood cells in typical sized rectangular microchannels. The test microchannel chips were fabricated by standard photolithography, ICP etching, and anode bonding with silicon wafers and glass covers. Flow field was magnified by an upright microscopy and images were captured by a high speed CCD camera. With a special designed image processing software, the images were filtered, enhanced, and edge detected for different purposes. The experiment results showed that the move and distribution of WBC in microchannel were significantly influenced by flow velocity, hematocrit, and other factors. The RBC occupy the center of channel and deform themselves to pass the narrow section of channel, in contrast to leukocyte, which deformed slightly and blocked the narrow section frequently. The measured results depicted that the deformability of blood cells subjected to many factors. This will be helpful in the design of blood cell separation devices and Keywords-



Standards related to Wafer bonding

Back to Top

No standards are currently tagged "Wafer bonding"


Jobs related to Wafer bonding

Back to Top