456 resources related to Vector processors
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2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting
The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science
The CDC is the premier conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, automatic control, and related areas.
APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics
IEEE International Conference on Plasma Science (ICOPS) is an annual conference coordinated by the Plasma Science and Application Committee (PSAC) of the IEEE Nuclear & Plasma Sciences Society.
The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.
The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.
Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.
Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.
Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...
Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.
IEEE Power Engineering Review, 1992
1993 IEEE International Conference on Acoustics, Speech, and Signal Processing, 1993
The concept of a variable-word-length sum-of-products signal processing kernel is developed based on a serial-by-modulus (SBM) residue number system (RNS) architecture. Because the RNS is not a weighted number representation, if the instantaneous dynamic range requirement can be estimated it is possible to perform the computation with only enough residue digits to provide the necessary dynamic range. Although it is ...
International Symposium on Innovations in Information and Communications Technology, 2011
This paper handle the design and implementation of the SIMD Vector Processor on FPGA, this processor consist of 4 parallel lanes (processing elements PEs) that work simultaneously independent with each other, each one of those lanes has its own arithmetic units, vector register file which represents a part of the main distributed register file also it has a local memory ...
The Sixth Distributed Memory Computing Conference, 1991. Proceedings, 1991
Seventh International Conference on Quality Software (QSIC 2007), 2007
SIMD (single instruction multiple data) is a processor architecture classification from Flynn's taxonomy. The concept is that a single instruction set operates on multiple units of data simultaneously. Computers use this processor architecture are known as array processors or vector processors. Most computers in use today are SISD (single instruction single data) though allowing a single instruction to operate on ...
IMS 2011 Microapps - Techniques for Validating a Vector Network Analyzer Calibration When Using Microwave Probes
IMS 2011 Microapps - IQ Mixer Measurements: Techniques for Complete Characterization of IQ Mixers Using a Multi-Port Vector Network Analyzer
IMS 2012 Microapps - Passive Intermodulation (PIM) measurement using vector network analyzer Osamu Kusano, Agilent CTD-Kobe
IMS 2012 Microapps - Basic Amplifier Measurements with the RF Vector Network Analyzer (VNA) Taku Hirato, Agilent
High Throughput Neural Network based Embedded Streaming Multicore Processors - Tarek Taha: 2016 International Conference on Rebooting Computing
Micro-Apps 2013: Alternative Methods and Optimization Techniques for Vector Modulation
MicroApps: 200W RF Power Amplifer Design using a Nonlinear Vector Network Analyzer and Measured Load-Dependent X-Parameters (2) (Agilent Technologies)
SIMD Programming in VOLK, the Vector-Optimized Library of Kernels
Vladimir Vapnik accepts the IEEE John Von Neumann Medal - Honors Ceremony 2017
Raspberry Pi High Speed SerDes Characterization Platform
Challenges and Opportunities of the NISQ Processors (Noisy Intermediate Scale Quantum Computing) - 2018 IEEE Industry Summit on the Future of Computing
Architecture and Dissipation: Thermodynamic Costs of General Purposeness in von Neumann Processors: IEEE Rebooting Computing 2017
Quantum Annealing: Current Status and Future Directions - Applied Superconductivity Conference 2018
The Josephson Effect: The Original SQUIDs
2017 IEEE Donald O. Pederson Award in Solid-State Circuits: Takao Nishitani and John S. Thompson
Going Beyond Moore's Law: IEEE at SXSW 2017
Micro-Apps Keynote 2013: Modern RF Measurements and How They Drive Spectrum Analyzer Digital IF Processor Design
Neural Processor Design Enabled by Memristor Technology - Hai Li: 2016 International Conference on Rebooting Computing
What members say about IEEE Communications Society
The concept of a variable-word-length sum-of-products signal processing kernel is developed based on a serial-by-modulus (SBM) residue number system (RNS) architecture. Because the RNS is not a weighted number representation, if the instantaneous dynamic range requirement can be estimated it is possible to perform the computation with only enough residue digits to provide the necessary dynamic range. Although it is difficult to estimate instantaneous dynamic range requirements for arbitrary computational processes encountered in general-purpose computers, in well-defined signal processing tasks, such as the sum-of-products kernel found in digital filters and vector processors, it may be possible to take advantage of a variable-word-length design to improve computational efficiency for special-purpose processors. Computer experiments were performed in software written in C that was designed to emulate an SBM FIR (finite impulse response) filter.<<ETX>>
This paper handle the design and implementation of the SIMD Vector Processor on FPGA, this processor consist of 4 parallel lanes (processing elements PEs) that work simultaneously independent with each other, each one of those lanes has its own arithmetic units, vector register file which represents a part of the main distributed register file also it has a local memory for storage of execution results of that lane, lanes's local memories connects to each other to exchange their contains via interconnection networking that can be configure software to give a certain topology of static interconnection network, like (Mesh, Star,...etc) those lanes and their memories act a vector part of the SIMD Vector Processor. A scalar processor also designed and attached with the vector part in order to accomplish scalar instructions that can not be handle by vector lanes, this processor also has its scalar register file and set of arithmetic units.
SIMD (single instruction multiple data) is a processor architecture classification from Flynn's taxonomy. The concept is that a single instruction set operates on multiple units of data simultaneously. Computers use this processor architecture are known as array processors or vector processors. Most computers in use today are SISD (single instruction single data) though allowing a single instruction to operate on multiple data can also be applied to a virtual machine that is capable of parallel execution through the use of multi-threading/multi-core processors, or distributed parallel execution on a multi-computer grid. This paper proposes a language structure that applies the SIMD concept to the Java virtual machine. The motive is to reduce the complexity of the code and ease implementation of parallelization by running a single set of instructions concurrently on an entire collection of objects.
Product requirements often dictate the use of off-the-shelf processors for very fast signal processing applications. Additionally, restrictions on cost, power, or size/weight may preclude the use of specialized vector processors for implementation of the algorithms. We discuss a new method for performing signed parallel processing in scalar, off-the-shelf processors for integerized signal processing algorithms. Uniform data precision may be used, but is not required for the method. It is shown that the reduction in execution cycles resulting from this implementation is approximately linear in the size of the registers, divided by the precision required.
Under the auspices of the mathematical software development contract with Fujitsu, a Fast Fourier transform library for the Fujitsu VPP500 has been implemented at the Australian National University. The software is written in modular form, using a library of Basic Fast Fourier Transform Subroutines (BAFFS) which derive from the splitting formula for a Fourier transform. Here, the expected performance of one of these BAFFS is examined for the VPP500 architecture, and some optimisations are outlined.<<ETX>>
The authors propose a simple modification to the conflict resolution scheme that will significantly improve the performance of the CRAY X-MP memory system. In particular, they show that it is possible to avoid linked conflicts due to a single CPU altogether by changing the priorities of active vector streams when a memory port encounters a memory bank conflict. Some examples are presented to show how the proposed scheme prevents these linked conflicts.<<ETX>>
Oxford Computer's A236 parallel digital signal processor chip is flexible, fully programmable and designed to compactly and inexpensively provide live video capture, processing and display. The use of single-chip, parallel processing with integrated data and instruction caches, and an inexpensive, high performance memory system, provide high performance at low cost. An extended, single-instruction multiple-data (SIMD) architecture with one, 24-bit scalar processor and four, 16-bit vector processors, is used. Five instructions are issued each clock cycle with a 40 MHz clock, providing up to 200 MIPS. Two, 16-bit, bi-directional, double-buffered, DMA ports support simultaneous video acquisition and display, and interface directly to common video decoder and encoder chips with no glue logic. A minimum system that provides all input and output frame buffering contains only three chips, an A236 Chip, a 32-bit wide, synchronous DRAM, and a serial I/sup 2/C EEPROM, plus analog video interface chips. A full set of software development tools that runs under MS Windows is available free, including an enhanced C-compiler that provides a simple method for representing parallel operations on data structures. An evaluation kit containing the software tools and the A236 Video Processing System I is also available.
Using a prime number p of memory banks on a vector processor allows a conflict-free access for any slice of p consecutive elements of a vector stored with a stride not multiple of p. To reject the use of a prime number of memory banks, it is generally advanced that address computation for such a memory system would require systematic Euclidean division by the number p. The Chinese Remainder Theorem allows a simple mapping of data onto the memory banks for which address computation does not require any Euclidean division. However, this requires that the number of words in each memory module m and p be relatively prime. We propose a method based on the Chinese Remainder Theorem for moduli with common factors that does not have such a restriction. The proposed method does not require Euclidean division and also results in an efficient error detection/correction mechanism for address translation.
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