Ultra large scale integration
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The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted full papers will be peer reviewed. Accepted high quality papers will be presented in oral and poster sessions,will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE.
The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.
the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.
The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.
The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...
Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
[1992 Proceedings] Electrical Performance of Electronic Packaging, 1992
1991 Symposium on VLSI Technology, 1991
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1990
A floorplanner, FOLM-planner, suitable for SOG gate arrays is presented. FOLM- planner is based on a 'frame overlapping floorplan model, which is free from unnecessary constraints caused by conventional floorplan models, and is easy to use for satisfying timing constraints. FOLM-planner aims at minimizing the net length among frames and controlling frame overlaps for efficient usage of a chip area. ...
Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on, 2002
To make a shallow junction, understanding the influence of the Si surface status is quite important to achieve stable-dose implanted layers. The causes or dose variation can be a sub-nm screening/capping oxide and silicon loss, which originate from the wet chemical processes, the photo resist processes and the clean room environment. These phenomena are examined using SIMS, sheet resistance and ...
Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135), 1998
Globecom 2019: Daniel Blumenthal Keynote
2015 IEEE Honors: IEEE-RSE James Clerk Maxwell Medal - Lynn Conway
Towards a distributed mm-scale chronically-implantable neural interface - IEEE Brain Workshop
Large Scale Data Mining Using Genetics-Based Machine Learning 3
Large Scale Data Mining Using Genetics-Based Machine Learning 1
Large Scale Data Mining Using Genetics-Based Machine Learning 2
KeyTalk with Ljubisa Stevanovic: From SiC MOSFET Devices to MW-scale Power Converters - APEC 2017
IEEE 5G Podcast with the Experts: 5G for large-scale wireless communications between autonomous vehicles
Designing Reconfigurable Large-Scale Deep Learning Systems Using Stochastic Computing - Ao Ren: 2016 International Conference on Rebooting Computing
Fast Scale Prototyping for Folded Millirobots
Flywheel Energy Storage for the 21st Century: APEC 2019
SDRJ: Small to Large Scale Quantum Computational Systems - Kae Nemoto at INC 2019
Zipline - IEEE Spectrum Technology in the Service of Society Award - 2019 IEEE Honors Ceremony
Multi-Level Optimization for Large Fan-In Optical Logic Circuits - Takumi Egawa - ICRC 2018
Interview with Matthew Fiedler—IEEE VIC Summit 2018
Micro-Apps 2013: Rapid Simulation of Large Phased Array T/R Module Networks
Neuromorphic computing with integrated photonics and superconductors - Jeffrey Shainline: 2016 International Conference on Rebooting Computing
Plenary: Creating Inflections - William Chappell - ICRC 2018
IEEE 5G World Forum 30 September - 02 October 2019 in Dresden Germany
A floorplanner, FOLM-planner, suitable for SOG gate arrays is presented. FOLM- planner is based on a 'frame overlapping floorplan model, which is free from unnecessary constraints caused by conventional floorplan models, and is easy to use for satisfying timing constraints. FOLM-planner aims at minimizing the net length among frames and controlling frame overlaps for efficient usage of a chip area. To accomplish these objectives, FOLM-planner uses a newly developed force directed method for frame reshaping as well as moving. Experimental results have shown that FOLM layout can shorten the net length inside a frame without the total net length becoming longer.<<ETX>>
To make a shallow junction, understanding the influence of the Si surface status is quite important to achieve stable-dose implanted layers. The causes or dose variation can be a sub-nm screening/capping oxide and silicon loss, which originate from the wet chemical processes, the photo resist processes and the clean room environment. These phenomena are examined using SIMS, sheet resistance and the transistor characteristics of a 90 nm node of high end CMOS logic device.
The advantages of SOI technologies in CMOS for rad-hard applications and for high performances are considered. The author discusses the need for rad-hard circuits beyond the military or space requirements.<<ETX>>
Thin film SOI technology has gained significant interest recently due to its potential application for ultra high density low power and radiation resistant electronics. Although significant progress has been made in reducing SIMOX defect density, the defects in SIMOX wafers are still important yield inhibitors to VLSI and ULSI circuits. Currently we are manufacturing large density SOI ASIC (400K usable gates) chips and 1M SOI SRAM chips including large 20 chip MCMs using SIMOX (BOX thickness /spl ap/380 nm). In this paper we describe our screening methods to achieve VLSI and ULSI circuit production with reasonable yield.
Summary form only given. The scaling of the CMOS channel length to below 0.5 /spl mu/m and increase of the chip density to the ULSI range have placed power dissipation on an equal footing with performance as a figure of merit in digital circuit design. Portability and reliability have also played a major role in the emergence of low-power, low-voltage, digital circuit designs. The need to extend the battery life, to have inexpensive packaging and cooling systems, and to reduce the weight and size of the equipment were the driving forces in this regard. Reducing the power dissipation of arithmetic operations while keeping the performance unaffected, is indispensable for digital signal processing (DSP), reduced instruction set computers (RISCs), microprocessors, etc. In this presentation, several novel high performance digital circuit designs that emphasize low-power and low-voltage operation are introduced. These circuits utilize a wide range of techniques that are used in state-of- the-art VLSI systems and hence serve as good examples for low-power design. In addition, important features of submicron VLSI technologies that support low- power operation of digital systems are discussed.
The current VLSI/ULSI technology enables the implementation of a complicated system in a single chip at a low cost. Thus it has become cost effective to design special-purpose multiprocessor architectures for computationally- intensive applications in signal processing, control of power systems and robotics. In this paper, we introduce a novel design methodology based on the problem-space genetic algorithms for the synthesis of application-specific multiprocessor systems to meet the various cost and performance constraints, not merely the mapping of tasks onto a given system. The design methodology for the synthesis of a custom heterogeneous multiprocessor system selects the number and type of processor, finds an interconnection pattern between processors, maps the subtasks onto the system and provides a static schedule for the subtasks execution for a given application specified in terms of a task flow graph. The proposed problem-space genetic algorithms (PSGA) based design methodology combines the power of genetic algorithms, a global search method, with a problem-specific efficient heuristic to search a large design space in an intelligent way in order to find a global optimal solution within acceptable cpu times. This paper applies a novel PSGA-based design methodology and achieves a considerable improvements in the cpu times over the previous works. Comparisons are made between our and the previous works to show the strength of our methodology for the applications of large sizes. For the same designs, our technique gives optimal results in seconds, while the previous approach gives same results in hours.<<ETX>>
Software reliability (SR) models have been evaluated and ranked for their applicability to various situations. Many improvements have been made in SR modeling and prediction since 1992. This revised recommended practice reflects those advances in SR since 1992, including modeling and prediction for distributed and network systems. Situation specific usage guidance was refined and updated. The methodologies and tools included ...
The project defines a standard for high-speed (>100 Mbps at the physical layer) communication devices via electric power lines, so-called broadband over power line (BPL) devices. This standard uses transmission frequencies below 100 MHz. It is usable by all classes of BPL devices, including BPL devices used for the first-mile/last-mile connection (<1500 m to the premise) to broadband services as ...
Physical connectors and cables, electrical properties, and logical protocols for point to point serial scaleable interconnect, operating at speeds of 10-200 Mbit/sec and at 1 Gbit/sec in copper and optic technologies (as developed in Open Microprocessor systems Initiative/heterogeneous InterConnect Project (OMI/HIC).