Conferences related to Systolic arrays

Back to Top

2018 IEEE 10th Sensor Array and Multichannel Signal Processing Workshop (SAM)

The SAM Workshop is an biennial IEEE Signal Processing Society event dedicated to sensor array and multichannel signal processing. It is managed by the Sensor Array and Multichannel Signal Processing Technical Committee of the IEEE Signal Processing Society.


2018 IEEE Canadian Conference on Electrical & Computer Engineering (CCECE)

CCECE is the flagship conference for researchers, students, and professionals in the area of Electrical and Computer Engineering from Canada and around the world to meet annually in a Canadian city to disseminate their research advancements and discoveries, to network and exchange ideas in order to strengthen existing partnerships and foster new collaborations


2018 IEEE International Conference on Consumer Electronics (ICCE)

The International Conference on Consumer Electronics (ICCE) is soliciting technical papersfor oral and poster presentation at ICCE 2018. ICCE has a strong conference history coupledwith a tradition of attracting leading authors and delegates from around the world.Papers reporting new developments in all areas of consumer electronics are invited. This year,papers relating Cybersecurity are particularly welcome.Topics around this major theme will be the content ofspecial sessions and tutorials.


2018 IEEE International Symposium on Circuits and Systems (ISCAS)

ISCAS is the world’s premier networking and exchange forum for leading researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS is the flagship conference of the IEEE Circuits and Systems Society and aim to bring together its multidisciplinary community that has a strong history of cultivating creative, proof-of-concept research in a diverse range of technical domains including analog and digital circuits and systems, nanotechnology, sensors, nonlinear systems, biosystems, neural systems, signal processing, and communications.


2018 IEEE International Workshop on Signal Processing Systems (SiPS)

CFP Areas of Technical Interest• VLSI Based Design and Implementation of Signal Processing Systems– Low-power signal processing circuits and applications– High performance VLSI systems– VLSI design for 100G and beyond networking systems– FPGA and reconfigurable architecture based systems– System-on-chip and network-on-chip– VLSI Systems for Wireless Sensor Network and RF Identification Systems• Software Based Design and Implementation of Signal Processing Systems– Programmable digital signal processor architecture and systems– Application specific instruction-set processor (ASIP) architecture and systems– SIMD, VLIW and multi-core CPU architecture– Graphic processing unit (GPU) based massively parallel implementation– Embedded FPGA architectures• Design Methods of Signal Processing Algorithms and Architectures– Optimization of signal processing algorithms– Compilers and tools for signal processing system design– Algorithm transformation and algorithm-to-architecture


More Conferences

Periodicals related to Systolic arrays

Back to Top

Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


More Periodicals

Most published Xplore authors for Systolic arrays

Back to Top

Xplore Articles related to Systolic arrays

Back to Top

Second International Specialist Seminar on the Design and Application of Parallel Digital Processors (Conf. Publ. No.334)

1991 Second International Specialist Seminar on the Design and Application of Parallel Digital Processors, 1991

None


Differential Scoring for Systolic Sequence Alignment

2007 IEEE 7th International Symposium on BioInformatics and BioEngineering, 2007

Systolic implementations of dynamic programming solutions that utilize a similarity matrix can achieve appreciable performance with both course-and fine-grain parallelization. A limitation of systolic array design is that score routing between array elements, array I/O bandwidth, and score memory capacity are dependent upon the length of the sequence that can be processed. A novel approach of differential scoring is presented ...


Processor array design for deep packet classification

Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004., 2004

We present several efficient systolic array architectures for string search for deep packet classification by using a procedural approach. We express the string search problem as a regular iterative algorithm. We also present a dependency graph from the iterative algorithm. From this dependency graph, we explore several systolic arrays for the string search algorithm. This methodology gives us the ability ...


Systolic implementation of FIR decimators and interpolators

IEE Proceedings - Circuits, Devices and Systems, 1994

An algebraic technique for mapping FIR decimator and interpolator algorithms with integer compression/expansion factors on systolic and semisystolic structures is described. The technique is based on the time-domain representation of the algorithms. The advantages of this technique are that it is suitable for describing multirate algorithms and that the required arithmetic operations are explicitly stated. Applying the algebraic technique, various ...


On-line arithmetic modules for recursive digital filters

[1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers, 1992

An online multiply-add (MA) module is designed for implementing second-order direct-form IIR filters. The MA module is implemented in a 0.7- mu m HCMOS gate array technology. An array of MA modules is developed to perform the second-order recursive computations at 128 Msamples/s with two levels of scattered lookahead. A conventional (bit-parallel) design using similar lookahead is implemented in the ...


More Xplore Articles

Educational Resources on Systolic arrays

Back to Top

IEEE.tv Videos

Array storing and retrieval
Array Representation
Random Sparse Adaptation for Accurate Inference with Inaccurate RRAM Arrays - IEEE Rebooting Computing 2017
Concept of Arrays
5G mmW Phased Arrays - Future X Radio Panel Talk - Baljit Singh - Brooklyn 5G Summit 2018
A 28GHz CMOS Direct Conversion Transceiver with Packaged Antenna Arrays for 5G Cellular Systems: RFIC Industry Showcase 2017
Micro-Apps 2013: Design and Simulation of Phased Arrays in VSS
5G UE Phased Array Design - Future X Radio Panel Talk - Ozge Koymen - Brooklyn 5G Summit 2018
Massive MIMO Active Antenna Arrays for Advanced Wireless Communications: IEEE CAS lecture by Dr. Mihai Banu
mmwave Phased Arrays for 5G Applications - Challenges and Opportunities - Ian Gresham: Brooklyn 5G Summit 2017
A 73GHz PA for 5G Phased Arrays in 14nm FinFET CMOS: RFIC Industry Showcase 2017
Abbas El Gamal accepts the IEEE Richard W. Hamming Medal - Honors Ceremony 2016
Brooklyn 5G - 2015 - Dr. Amitabha Ghosh & Dr. Timothy A. Thomas - 5G Channel Modeling from 6 to 100 GHz: Critical Modeling Aspects and Their Effect on System Design and Performance
CASS Lecture by Dr. Chris Hull, "Millimeter-Wave Power Amplifiers in FinFET Technology"
A Comparator Design Targeted Towards Neural Net - David Mountain - ICRC San Mateo, 2019
The Josephson Effect: The Josephson Volt
Laser Communication From Space Using Superconducting Detectors - ASC-2014 Plenary series - 12 of 13 - Friday 2014/8/15
Day 1, PM Sessions Part 1- Brooklyn 5G Summit 2018
Micro-Apps 2013: Rapid Simulation of Large Phased Array T/R Module Networks
2011 IEEE Medal for Innovations in Healthcare Technology - Harrison H. Barrett

IEEE-USA E-Books

  • Second International Specialist Seminar on the Design and Application of Parallel Digital Processors (Conf. Publ. No.334)

    None

  • Differential Scoring for Systolic Sequence Alignment

    Systolic implementations of dynamic programming solutions that utilize a similarity matrix can achieve appreciable performance with both course-and fine-grain parallelization. A limitation of systolic array design is that score routing between array elements, array I/O bandwidth, and score memory capacity are dependent upon the length of the sequence that can be processed. A novel approach of differential scoring is presented that exploits adjacency and decouples the complexity of score routing and systolic array bandwidth to sequence length. Instead, these design parameters become a function of algorithm sensitivity. As a consequence, the Simile implementation of differential scoring for sequence alignment has reduced score routing, I/O bandwidth, and score storage by 82% for sequences of length 10 and has significantly improved gate count, clock rate, and power utilization per systolic processing element.

  • Processor array design for deep packet classification

    We present several efficient systolic array architectures for string search for deep packet classification by using a procedural approach. We express the string search problem as a regular iterative algorithm. We also present a dependency graph from the iterative algorithm. From this dependency graph, we explore several systolic arrays for the string search algorithm. This methodology gives us the ability to pipeline some variables and broadcast other variables. This allows optimizing the architecture for speed, area and other design requirements. The proposed designs exhibit optimum speed and area complexities.

  • Systolic implementation of FIR decimators and interpolators

    An algebraic technique for mapping FIR decimator and interpolator algorithms with integer compression/expansion factors on systolic and semisystolic structures is described. The technique is based on the time-domain representation of the algorithms. The advantages of this technique are that it is suitable for describing multirate algorithms and that the required arithmetic operations are explicitly stated. Applying the algebraic technique, various structures can be obtained in which the number of multipliers is reduced in proportion to the decimation or interpolation factor. Pipelining can be introduced at the input and/or the output. An example is given to illustrate the flexibility and simplicity of the proposed technique.<<ETX>>

  • On-line arithmetic modules for recursive digital filters

    An online multiply-add (MA) module is designed for implementing second-order direct-form IIR filters. The MA module is implemented in a 0.7- mu m HCMOS gate array technology. An array of MA modules is developed to perform the second-order recursive computations at 128 Msamples/s with two levels of scattered lookahead. A conventional (bit-parallel) design using similar lookahead is implemented in the same technology. The 104-Msample/s conventional design implements a carry-free recursive loop and uses radix-4 recoding to reduce the number of partial products. The online array has a sampling rate higher than the conventional implementation for 12 or more bits.<<ETX>>

  • A bit-serial systolic algorithm and VLSI implementation for RSA

    A new algorithm using delayed save adder representation and overflow determination technique for modular multiplication is presented. This algorithm can be implemented by a bit-serial systolic array for modular multiplications. A two level bit-serial systolic array for RSA is also designed and implemented. Our simulation and experimental chip design show that the proposed algorithm and its bit-serial implementation is suitable for VLSI, and a single RSA chip can be built to achieve much higher throughput.

  • Synthesis of a systolic array genetic algorithm

    The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demonstrated is the design methodology where a simple genetic algorithm expressed in C source code is progressively re- written into a recurrence form from which systolic structures can be deduced. The paper extends previous work by the authors by introducing a simplification to a previous systolic design.

  • Recursive LS filtering using block Householder transformations

    A systolic block Householder transformation is proposed to implement the HT (Householder transformation) on a systolic array as well as to apply it to the RLS algorithm. Since the data are fetched in a block manner, vector operations are in general required for the vectorized array. The approach makes the HT suitable for VLSI implementation as well as applicable to real-time high- throughput applications of modern signal processing.<<ETX>>

  • A technique for unsupervised cluster recognition

    A methodology is presented for solving a basic problem in pattern recognition, that of unsupervised data clustering. Let X=(x/sub i/) denote a finite subset of the vector space S. Using a metric criterion, and with no prior information, determine the existence of clusters in the set X. Further, determine the number of clusters, the cluster membership of each point of X, and consequently a disjoint decomposition of X. Finally, if X is a moving window on a possibly infinite data stream, can these matters be resolved online? The design of the methodology given has features which are compatible with systolic array implementation and, in particular, VLSI technology. The performance of the design is evaluated using a simulation testbed. Some alternative techniques, based on SAS statistical software, are also explored and comparison with the resultant designs is given.<<ETX>>

  • Run-time error detection in arrays based on the data-dependency graph

    ITRED (input-driven time-redundancy error detection), a methodology based on dependency graphs for doing concurrent run-time error detection in systolic arrays and wavefront processors, is described. It combines the projection method of deriving systolic arrays from dependency graphs with the idea of input-triggered testing. Tests are triggered by inserting special symbols in the input, and so the approach gives the user flexibility in trading off throughput for error coverage. Correctness of timing is proved at the dependency graph level. The method requires no extra processing elements and little extra hardware. The general approach is presented, and corresponding constraints on the modified dependency graphs that guarantee correctness are derived.<<ETX>>



Standards related to Systolic arrays

Back to Top

No standards are currently tagged "Systolic arrays"


Jobs related to Systolic arrays

Back to Top