# Summing circuits

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### Conferences related to Summing circuits

2023 Annual International Conference of the IEEE Engineering in Medicine & Biology Conference (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted full papers will be peer reviewed. Accepted high quality papers will be presented in oral and poster sessions,will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE.

2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology

2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation

### Periodicals related to Summing circuits

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

### Xplore Articles related to Summing circuits

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1987

An MOS analog multiplier based on the square law algebraic identity will be covered. The multiplier achieves a nonlinearity of 9.44%, a bandwidth of 5MHz, dynamic range of 87dB and total harmonic distortion of 0.59%. The chip was fabricated with a 5&#956;m P-well CMOS process. Size is 500mil<sup>2</sup>and total power consumption is 10mW.

2007 7th International Conference on ASIC, 2007

This paper describes a new approach for design and implementation of programmable voltage reference based on current mode bandgap voltage reference and a proportional summing circuit. The circuit is simulated and fabricated with Chartered 0.35 um mixed-signal technology, and our measurements demonstrate that its temperature coefficient is plusmn35.07 ppm/degC from 0 to 100degC. The supply voltage is varied from 2.7-5 ...

2018 IEEE East-West Design & Test Symposium (EWDTS), 2018

The CMOS logical element of matching contains the STG DICE memory cell with transistors divided into two groups together with transistors of the output combinational logic. A single nuclear particle generates charges along its track. The collection of an induced charge just one group of transistors does not lead to the failure of the logical state of the cell. The ...

IEEE Transactions on Communications, 1977

A phase modulator is described which deviates from perfect linearity by ± 1 degree maximum in the range± 90 degrees. It can be adjusted to eliminate third order distortion. A digital application is illustrated.

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1995

This paper describes a programmable 3-V CMOS rail-to-rail opamp with gain boosting. The unity-gain frequency can be programmed from 0.5 to 4 MHz, for a load of 50 pF, by changing the supply current from 55 to 390 /spl mu/A. The g/sub m/-control of the input stage functions regardless of its operating region, whether it is weak or strong inversion. ...

### Educational Resources on Summing circuits

#### IEEE-USA E-Books

• An MOS analog multiplier based on the square law algebraic identity will be covered. The multiplier achieves a nonlinearity of 9.44%, a bandwidth of 5MHz, dynamic range of 87dB and total harmonic distortion of 0.59%. The chip was fabricated with a 5&#956;m P-well CMOS process. Size is 500mil<sup>2</sup>and total power consumption is 10mW.

• This paper describes a new approach for design and implementation of programmable voltage reference based on current mode bandgap voltage reference and a proportional summing circuit. The circuit is simulated and fabricated with Chartered 0.35 um mixed-signal technology, and our measurements demonstrate that its temperature coefficient is plusmn35.07 ppm/degC from 0 to 100degC. The supply voltage is varied from 2.7-5 V and the varied voltage reference is about 5 mV. Depending on the state of the five VID inputs, an output voltage between 1.075 V and 1.85 V is programmed in 25 mV increments.

• The CMOS logical element of matching contains the STG DICE memory cell with transistors divided into two groups together with transistors of the output combinational logic. A single nuclear particle generates charges along its track. The collection of an induced charge just one group of transistors does not lead to the failure of the logical state of the cell. The results of the simulation presents for the element of matching as a part of an associative memory. It shows the hardness to a fault of the cell up to 70 MeV×cm2/mg of the linear energy transfer on the tracks of single particles. Noise pulses generate mostly in the output logic at the mode when the output has to be equal “1”. The correct results of matching data in registers of cells, when a noise pulse is, get more reliable using the summing circuits on the combinational logic but not using match lines.

• A phase modulator is described which deviates from perfect linearity by ± 1 degree maximum in the range± 90 degrees. It can be adjusted to eliminate third order distortion. A digital application is illustrated.

• This paper describes a programmable 3-V CMOS rail-to-rail opamp with gain boosting. The unity-gain frequency can be programmed from 0.5 to 4 MHz, for a load of 50 pF, by changing the supply current from 55 to 390 /spl mu/A. The g/sub m/-control of the input stage functions regardless of its operating region, whether it is weak or strong inversion. This allows an optimal frequency compensation over the total programming range. The opamp features a low-voltage gain-boosting technique which provides a high gain of about 120 dB, even for loads of 50 /spl Omega/. The opamp has been designed in a 1 /spl mu/m BiCMOS process.

• The 5-tap FIR structure uses 3rd-order linear-phase cells to implement delays of 500ps for a T/2 fractionally-spaced equalizer. To improve the bandwidth of the summing circuit, the design incorporates a transimpedance load, increasing the bandwidth by a factor of 3.6 over a conventional resistive load. The equalizer consumes 96mW with plusmn1.5V and occupies 0.26mm<sup>2</sup> in a CMOS 0.35mum process.

• A low-voltage and low-power Delta Sigma modulator is presented in this paper. The modulator employs a third-order single-loop topology with feed-forward path and a single-bit quantizer. The summing circuit becomes simpler in single-bit modulator, which avoids an extra amplifier and decreases power dissipation by getting rid of the traditional switch-capacitor-amplifier style in multi-bit output structure. By utilizing the advanced switched- capacitor(SC) integrator topology especially designed for the technology of zeros optimization, the huge difference between capacitors due to the small zero feedback coefficient is improved, which can save the chip area efficiently. The modulator, designed in SMIC 0.18-μm CMOS process, achieves a 93 dB signal to noise ratio (SNR) in a 1 KHz signal bandwidth and consumes 1.35 mW from a 1.5 V supply.

• A conferencing scheme based on signal addition has been presented. Use of alternating inverting amplifier stages at the summing circuits considerably cancels out the effect of feedback voltages due to poor return loss of the hybrids. In the worst case, the net feedback voltage due to return loss at any subscriber line circuit is no more than twice than that encountered in one-to- one connection.

• Recently, correlation functions have had to be considered where both the reference waveform, which is usually the desired signal, and the input waveform are masked by different samples of additive noise. In this article, we derive the probability density function for the random variable<tex>\beta</tex>where $$\beta = \sum_{i=1}^k (As_{i,x} + N_{i,x})(Bs_{i,y} + N_{i,y}).$$ The<tex>s_{i,x}</tex>and<tex>s_{i,y}</tex>are the signal components, and<tex>N_{i,x}</tex>and<tex>N_{i,y}</tex>are samples of Gaussian noise. Exact expressions involving Bessel and Whittaker functions are given for several cases. Asymptotic expressions allow<tex>W(\beta)</tex>to be plotted when these exact expressions cannot be obtained or conveniently evaluated.

• A design for a four-quadrant analog multiplier using GaAs MESFET transistors is presented. The circuit permits operation at frequencies up to 1.0 gigahertz with errors less than 1% with inputs varying over a range -0.6 V<or=V/sub in/<or=0.6 V. The static power dissipated by the circuit is 138 mW. The author includes principles of operation and an estimate of accuracy, complete details of the multiplier circuitry, and the results of a SPICE simulation.<<ETX>>