Conferences related to Sum product algorithm

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ICC 2021 - IEEE International Conference on Communications

IEEE ICC is one of the two flagship IEEE conferences in the field of communications; Montreal is to host this conference in 2021. Each annual IEEE ICC conference typically attracts approximately 1,500-2,000 attendees, and will present over 1,000 research works over its duration. As well as being an opportunity to share pioneering research ideas and developments, the conference is also an excellent networking and publicity event, giving the opportunity for businesses and clients to link together, and presenting the scope for companies to publicize themselves and their products among the leaders of communications industries from all over the world.


2020 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

CVPR is the premier annual computer vision event comprising the main conference and several co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry researchers.

  • 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premier annual computer vision event comprising the main conference and severalco-located workshops and short courses. With its high quality and low cost, it provides anexceptional value for students, academics and industry researchers.

  • 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premier annual computer vision event comprising the main conference and several co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry researchers.

  • 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conferenceand 27co-located workshops and short courses. With its high quality and low cost, it provides anexceptional value for students,academics and industry.

  • 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry.

  • 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    computer, vision, pattern, cvpr, machine, learning

  • 2014 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. Main conference plus 50 workshop only attendees and approximately 50 exhibitors and volunteers.

  • 2013 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry.

  • 2012 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Topics of interest include all aspects of computer vision and pattern recognition including motion and tracking,stereo, object recognition, object detection, color detection plus many more

  • 2011 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Sensors Early and Biologically-Biologically-inspired Vision, Color and Texture, Segmentation and Grouping, Computational Photography and Video

  • 2010 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Concerned with all aspects of computer vision and pattern recognition. Issues of interest include pattern, analysis, image, and video libraries, vision and graphics, motion analysis and physics-based vision.

  • 2009 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Concerned with all aspects of computer vision and pattern recognition. Issues of interest include pattern, analysis, image, and video libraries, vision and graphics,motion analysis and physics-based vision.

  • 2008 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2007 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2006 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2005 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)


2020 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2020, the 27th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


GLOBECOM 2020 - 2020 IEEE Global Communications Conference

IEEE Global Communications Conference (GLOBECOM) is one of the IEEE Communications Society’s two flagship conferences dedicated to driving innovation in nearly every aspect of communications. Each year, more than 2,900 scientific researchers and their management submit proposals for program sessions to be held at the annual conference. After extensive peer review, the best of the proposals are selected for the conference program, which includes technical papers, tutorials, workshops and industry sessions designed specifically to advance technologies, systems and infrastructure that are continuing to reshape the world and provide all users with access to an unprecedented spectrum of high-speed, seamless and cost-effective global telecommunications services.


ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

The ICASSP meeting is the world's largest and most comprehensive technical conference focused on signal processing and its applications. The conference will feature world-class speakers, tutorials, exhibits, and over 50 lecture and poster sessions.


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Periodicals related to Sum product algorithm

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Broadcasting, IEEE Transactions on

Broadcast technology, including devices, equipment, techniques, and systems related to broadcast technology, including the production, distribution, transmission, and propagation aspects.


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


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Most published Xplore authors for Sum product algorithm

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Xplore Articles related to Sum product algorithm

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Overlapped decoding for a class of quasi-cyclic LDPC codes

IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004., 2004

In low-density parity-check (LDPC) code decoding with the iterative sum- product algorithm (SPA), due to the randomness of the parity-check matrix, H, the overlapping of the check node processing unit (CNU) and variable node processing unit (VNU) in the same clock cycle is difficult. The paper demonstrates that overlapped decoding can be exploited as long as the LDPC matrix is ...


LDPC Codes of Arbitrary Girth

2007 10th Canadian Workshop on Information Theory (CWIT), 2007

For regular, degree two LDPC (low density parity-check) codes, there is a strong relationship between high girth and performance. This article presents a greedy algorithm, called successive level growth (SLG), for the construction of LDPC codes with arbitrarily specified girth. The simulation results show that our codes exhibit significant coding gains over randomly constructed LDPC codes and in some cases ...


Construction of Quasi-Cyclic LDPC Codes Based on the Primitive Elements of Finite Fields

2006 40th Annual Conference on Information Sciences and Systems, 2006

This paper presents an algebraic method for constructing quasi-cyclic LDPC codes based on the primitive elements of finite fields. The construction gives a class of efficiently encodable quasi-cyclic LDPC codes. Experimental results show that the constructed codes decoded with iterative decoding using the sum- product algorithm perform well over the AWGN channel.


A Low-Complexity Layered Decoding Algorithm for LDPC Codes

2009 International Forum on Computer Science-Technology and Applications, 2009

A Low-complexity Layered Decoding Algorithm for LDPC Codes is proposed. Our modified algorithm reduces the number of operations in variable nodes to lower LDPC decoder power consumption. The modified parts of LDPC decoder architecture is also described. Simulation results show that comparing with SPA and MSA, our algorithm reducing the number of operations nearly to 60% with little performance loss.


Geometry based designs of LDPC codes

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577), 2004

In this paper we construct three types of low-density parity-check codes with column weight j = 3 based on geometries in graphical models. Low-density parity-check codes with j > 2 are desired because their minimum distance improves linearly with the code block length n. The codes we present here have girth 8 and girth 10. All codes are regular and ...


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Educational Resources on Sum product algorithm

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IEEE-USA E-Books

  • Overlapped decoding for a class of quasi-cyclic LDPC codes

    In low-density parity-check (LDPC) code decoding with the iterative sum- product algorithm (SPA), due to the randomness of the parity-check matrix, H, the overlapping of the check node processing unit (CNU) and variable node processing unit (VNU) in the same clock cycle is difficult. The paper demonstrates that overlapped decoding can be exploited as long as the LDPC matrix is composed of identity matrices and their cyclic-shifted matrices, i.e., the parity-check matrix, H, belongs to a class of quasi-cyclic LDPC codes. It is shown that the number of clock cycles required for decoding can be reduced by 50% when overlapped decoding is applied to a (3,6)-regular LDPC code decoder.

  • LDPC Codes of Arbitrary Girth

    For regular, degree two LDPC (low density parity-check) codes, there is a strong relationship between high girth and performance. This article presents a greedy algorithm, called successive level growth (SLG), for the construction of LDPC codes with arbitrarily specified girth. The simulation results show that our codes exhibit significant coding gains over randomly constructed LDPC codes and in some cases outperform PEG codes in the additive white Gaussian noise channel.

  • Construction of Quasi-Cyclic LDPC Codes Based on the Primitive Elements of Finite Fields

    This paper presents an algebraic method for constructing quasi-cyclic LDPC codes based on the primitive elements of finite fields. The construction gives a class of efficiently encodable quasi-cyclic LDPC codes. Experimental results show that the constructed codes decoded with iterative decoding using the sum- product algorithm perform well over the AWGN channel.

  • A Low-Complexity Layered Decoding Algorithm for LDPC Codes

    A Low-complexity Layered Decoding Algorithm for LDPC Codes is proposed. Our modified algorithm reduces the number of operations in variable nodes to lower LDPC decoder power consumption. The modified parts of LDPC decoder architecture is also described. Simulation results show that comparing with SPA and MSA, our algorithm reducing the number of operations nearly to 60% with little performance loss.

  • Geometry based designs of LDPC codes

    In this paper we construct three types of low-density parity-check codes with column weight j = 3 based on geometries in graphical models. Low-density parity-check codes with j > 2 are desired because their minimum distance improves linearly with the code block length n. The codes we present here have girth 8 and girth 10. All codes are regular and well-structured. These codes have flexible block lengths and code rates, and may be used in the area of communications and data storage. Our simulation results show that they have better bit-error-rate decoding performance and lower error floors in additive white Gaussian noise channels than randomly constructed low-density parity- check codes.

  • Adaptive quantization in min-sum based irregular LDPC decoder

    In this paper, we present adaptive quantization schemes in the normalized min- sum decoding algorithm considering scaling effects to improve the performance of irregular low-density parity-check (LDPC) decoder for WirelessMAN (IEEE 802.16e) applications. We discuss the finite precision effects on the performance of irregular LDPC codes and develop optimal finite word lengths of variables over an SNR. For floating point simulation, it is known that in the normalized min-sum or offset min-sum algorithms the performance of a min-sum based decoder is not sensitive to scaling in the log-likelihood ratio (LLR) values. However, when considering the finite precision for hardware implementation, the scaling affects the dynamic range of the LLR values. The proposed adaptive quantization approach provides the optimal performance in selecting suitable input LLR values to the decoder as far as the tradeoffs between error performance and hardware complexity are concerned.

  • Is BCH decoder really necessary in DVB-T2 receiver

    The digital video broadcasting-second generation terrestrial (DVB-T2) uses both low-density parity check (LDPC) and BCH error-correction codes. Since the LPDC decoder can correct more errors with more iterations, it is important to know the advantage of using the BCH decoder in a DVB-T2 receiver. This paper addresses this issue and gives some simulation results. The results show that at higher SNR environment, the BCH decoder may not be necessary.

  • New algorithm for 2D barcode detection

    In this paper we propose a new two dimensional (2D) barcode detection algorithm. This algorithm can generally be proposed for high density codes with very small projected image. This algorithm is a simplified expression of the sum product algorithm (SPA). We apply it in a joint detection and decoding structure and then we will compare it with known 2D barcode decoding technique.

  • Partition-and-shift LDPC codes

    This paper describes a new type of regular structured low-density parity-check (LDPC) code: the partition-and-shift LDPC (PS-LDPC) code. PS-LDPC codes can be easily designed to have large girth. The code construction is simple to explain: we divide the bit and check nodes in the Tanner graph into subsets and connect nodes in these subsets according to a set of parameters called shifts. We derive a general theorem on the shifts to prevent cycles that are harmful to LDPC decoding. This theorem provides a methodology to design PS- LDPC codes with arbitrary column weight j and large girth g. Simulation results over EPR4 channels demonstrate the good bit-error rate performance of PS-LDPC codes.

  • LDPC codes and stochastic decoding for beyond 100 Gb/s optical transmission

    We present a modified stochastic LDPC decoding algorithm suitable for implementation at 100-Gb/s and above. The stochastic decoding is invented for low-precision digital circuits, and as such is suitable for beyond 100-Gb/s implementation to avoid the problem of nonexistence of high-precision analog- to-digital converters operating at those speeds.



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