886 resources related to Subthreshold current
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the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
The IEEE Custom Integrated Circuits Conference (CICC) is the premier conference devoted to IC development. CICC emphasizes the education of experienced engineers as well as students while showcasing original, first-published innovative analog and digital circuit techniques covering a broad spectrum of technical topics. It is a forum for circuit, IC and SoC designers, CAD developers, manufacturers and ASIC users. CICC is the conference to find out how to solve design problems and improve circuit design and chip design techniques.
Analog Circuits, Digital VLSI Circuits, Neural Networks, Non-Linear System, Computer Aided Design, Communication Systems, Digital Signal Processing, MEMS, Nano-electronics
ISCAS is the world’s premier networking and exchange forum for leading researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS is the flagship conference of the IEEE Circuits and Systems Society and aim to bring together its multidisciplinary community that has a strong history of cultivating creative, proof-of-concept research in a diverse range of technical domains including analog and digital circuits and systems, nanotechnology, sensors, nonlinear systems, biosystems, neural systems, signal processing, and communications.
NEWCAS2018 will encompass a wide range of special sessions and keynote talks given by prominent expertscovering key areas of research in microsystems in order to provide all attendees a unique forum for the exchange of ideas and results. The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared by researchers in this field.
The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...
Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
 49th Annual Device Research Conference Digest, 1991
27th European Solid-State Device Research Conference, 1997
2005 IEEE Asian Solid-State Circuits Conference, 2005
A 128Mb pseudo SRAM is developed using a special type of architecture with the purpose of effectively reducing the standby current. Standby current, especially the off leakage current is becoming more difficult problem to handle in modern devices because shorter channel length in high density and high speed devices are at a point where off leakage is the major source. ...
Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005., 2005
In this paper, 90 nm MOSFET subthreshold hump characteristics are reported for the first time by using a newly developed MOSFET array test structure, which has small-scale DUTs with a new layout pattern, in order to eliminate the influence of gate leakage and off leakage on measured MOSFET parameter data such as Vth, Ion, subthreshold slope, etc. It is confirmed ...
Proceedings of the 26th European Solid-State Circuits Conference, 2000
Based on the study about the previously developed back-bias generators, a new high-efficiency back-bias generator with the Cross-coupled Hybrid Pumping Circuit 2 (CHPC2) is presented in this paper. CHPC2 takes only the advantages from the previous ones, throwing away the disadvantages. CHPC2 shows |V<inf>BB</inf>|/V<inf>CC</inf>as large as 98% even at low V<inf>CC</inf>=0.9 V, strongly addressing that it will be suitable at ...
ITEC 2014: Urban Mass Transit Systems: Current Status and Future Trends
Innovative Mechanical Systems to Address Current Robotics Challenges
IEEE PES Awards 2020: IEEE PES Uno Lamm High Voltage Direct Current Award
"Towards Monolithic Quantum Computing Processors In Production FDSOI CMOS Technology"
APEC 2012 - Dr. Fred Lee Plenary
APEC 2015: 3D Packaging
ITEC 2014: Electrifying Marine: Full Current Ahead - Clean, Efficient, Reliable and Quiet
DualCool NexFET Power MOSFETs
On the Characterization of Thermal Coupling Resistance in a Current Mirror: RFIC Industry Showcase 2016
A 12-b, 1-GS/s 6.1mW Current-Steering DAC in 14nm FinFET with 80dB SFDR for 2G/3G/4G Cellular Application: RFIC Industry Showcase 2017
TechFlash with Stefano Zanero - IEEE Young Professionals
High-current HTS cables for magnet applications - ASC-2014 Plenary series - 8 of 13 - Thursday 2014/8/14
A Conversation with Danielle Bassett: IEEE TechEthics Interview
Electric Motorcycle Races at Pikes Peak International - IEEE Spectrum Report
Robotics History: Narratives and Networks Oral Histories: Ruzena Bajcsy
Industry Forum: 5G Technologies and Applications, Joseph Salvo - IECON 2018
Spin Dynamics in Inhomogeneously Magnetized Systems - Teruo Ono: IEEE Magnetics Society Distinguished Lecture 2016
Inspiring Brilliance: Celebrating the Legacy of James Clerk Maxwell
Memristor: 37 Years Later
A 128Mb pseudo SRAM is developed using a special type of architecture with the purpose of effectively reducing the standby current. Standby current, especially the off leakage current is becoming more difficult problem to handle in modern devices because shorter channel length in high density and high speed devices are at a point where off leakage is the major source. In order to solve this issue, hyper destructive read architecture (HyDRA) is developed. HyDRA is a special DRAM architecture enabling destructive reading of DRAM cells using global bitline and extra tag memory. The paper demonstrates HyDRA utilizing its fast row cycle capability to instead minimize standby power to 150muA @ 2.1V and 90degC while maintaining the speed and chip area of the conventional scheme using the same process technology
In this paper, 90 nm MOSFET subthreshold hump characteristics are reported for the first time by using a newly developed MOSFET array test structure, which has small-scale DUTs with a new layout pattern, in order to eliminate the influence of gate leakage and off leakage on measured MOSFET parameter data such as Vth, Ion, subthreshold slope, etc. It is confirmed that a subthreshold hump occurs at random in an array, and the hump occurrence percentage differs with chips in a wafer. By extracting the hump variation with a MOSFET array, it is possible to estimate accurately and reduce the standby-current in logic LSI chips.
Based on the study about the previously developed back-bias generators, a new high-efficiency back-bias generator with the Cross-coupled Hybrid Pumping Circuit 2 (CHPC2) is presented in this paper. CHPC2 takes only the advantages from the previous ones, throwing away the disadvantages. CHPC2 shows |V<inf>BB</inf>|/V<inf>CC</inf>as large as 98% even at low V<inf>CC</inf>=0.9 V, strongly addressing that it will be suitable at low voltage DRAM applications. Moreover, CHPC2 exhibits much better pumping efficiency and larger pumping current over the previous ones with wide R<inf>L</inf>range at V<inf>CC</inf>=1.2 V.
A novel pass transistor design methodology to optimize gate oxide thickness (t/sub ox/), booted wordline voltage (V/sub WL/), substrate bias (V/sub sub/), and processing conditions is presented in this paper. It is found that for a gate length of 0.3 /spl mu/m a t/sub ox/ of about 85 /spl Aring/ (which is much thicker than the /spl sim/65 /spl Aring/ t/sub ox/ for 0.25 /spl mu/m logic technology) to support a V/sub WL/ of 3.75 V, a V/sub sub/ of about -1 V, and As LDD are the optimum technological choices for 256 Mbit DRAM.<<ETX>>
This paper describes the dependence of MOSFET gate-controllability on the field isolation scheme. It is found that a fully-recessed oxide (trench) isolated MOSFET has a sharp cutoff characteristic and high transconductance in comparison with a non-recessed one. These features of the fully-recessed oxide MOSFET are due to the crowding of the gate's fringing field at the channel edge. It is also found that the gate and diffused line capacitances for the fully-recessed oxide isolation are small so that high switching speed operation can be expected.
By accounting for the effects of equivalent oxide charges on the flat-band voltage, a novel interface-trapped-charge-degraded subthreshold current model is presented for the quadruple-gate (QG) MOSFETs based on the quasi-3-D scaling equation and Pao-Sah's integral. It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the trapped charges. In contrast to the thin gate oxide, a thick silicon film is required to alleviate the subthreshold current degradation caused by the negative trapped charges. For the short-channel behavior, the damaged device with negative and positive trapped charges can decrease and increase subthreshold current roll up caused by the short-channel effects, respectively. Due to computational efficiency, the model can be easily used to explore the hot-carrier-induced current behavior for the fully depleted QG MOSFETs for its memory cell application.
The aim of this paper is to design analog circuits which develop different computations. This work generalizes the basic idea of the implementation of squaring and square root circuits proposed before to generate nth-power-law circuits and nth-root circuits. The MOSFET's work on the weak inversion region which allows implementing different kinds of non-linear functions. Fundamental circuit operations were demonstrated and the performance of the circuits using SPICE (simulation program with integrated circuit emphasis) was confirmed. The design was developed for a 0.5 ¿m-technology.
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