Conferences related to Substrate hot electron injection

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2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE 11th International Memory Workshop (IMW)

The IMW is a unique forum for specialists in all aspects of memory (nonvolatile & volatile)microelectronics and people with different backgrounds who wish to gain a better understandingof the field. The morning and afternoon technical sessions are organized in a manner thatprovides ample time for informal exchanges amongst presenters and attendees. The eveningpanel discussions will address hot topics in the memory and memory system field. Papers aresolicited in all aspects of semiconductor memory technology (Flash, DRAM, SRAM, PCRAM,RRAM, MRAM, embedded memory, and other NV memories).


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


2019 IEEE Photonics Conference (IPC)

The IEEE Photonics Conference, previously known as the IEEE LEOS Annual Meeting, offers technical presentations by the world’s leading scientists and engineers in the areas of lasers, optoelectronics, optical fiber networks, and associated lightwave technologies and applications. It also features compelling plenary talks on the industry’s most important issues, weekend events aimed at students and young photonics professionals, and a manufacturer’s exhibition.


2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAM


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Periodicals related to Substrate hot electron injection

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Dielectrics and Electrical Insulation, IEEE Transactions on

Electrical insulation common to the design and construction of components and equipment for use in electric and electronic circuits and distribution systems at all frequencies.


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


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Most published Xplore authors for Substrate hot electron injection

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Xplore Articles related to Substrate hot electron injection

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Back-bias Enhanced Source-Side Injection in 0.25um Embedded Flash Memories

29th European Solid-State Device Research Conference, 1999

None


New programming and erasing schemes for p-channel flash memory

IEEE Electron Device Letters, 2000

In this work, a new programming scheme using a forward substrate bias during BBHE injection and a two-step erasing scheme has been suggested to improve the performances of p-channel flash memory. It has been found that applying a forward substrate bias increases the electron injection efficiency and improves the cell's endurance characteristics. The two-step erasing scheme, where a channel erase ...


VIPMOS, a Buried Local Injector for EPROMs

ESSDERC '89: 19th European Solid State Device Research Conference, 1989

A highly effective substrate hot electron injection EPROM device can be made using a buried injector, which operates in punch-through mode. The buried injector is formed by a local overlap of the N-well and P-well of a retrograde twin-well CMOS-process. As the VIPMOS-EPROM is compatible with VLSI-processing and the danger of latch-up doesn't exist, the VIPMOS-structure may be used in ...


Hot electron improvement in MOS RAM's based on epitaxial substrate

1982 International Electron Devices Meeting, 1982

None


A better understanding of substrate enhanced gate current in VLSI MOSFET's and flash cells. I. Phenomenological aspects

IEEE Transactions on Electron Devices, 1999

This paper analyzes in depth the phenomenon of gate current enhancement upon application of a substrate voltage (|V/sub B/|) recently observed in deep submicron MOSFETs. The correlation between the gate (I/sub G/) and the substrate (I/sub B/) current is studied as a function of |V/sub B/|, and it is shown: (1) to provide an experimental signature of the onset of ...


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Educational Resources on Substrate hot electron injection

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IEEE-USA E-Books

  • Back-bias Enhanced Source-Side Injection in 0.25um Embedded Flash Memories

    None

  • New programming and erasing schemes for p-channel flash memory

    In this work, a new programming scheme using a forward substrate bias during BBHE injection and a two-step erasing scheme has been suggested to improve the performances of p-channel flash memory. It has been found that applying a forward substrate bias increases the electron injection efficiency and improves the cell's endurance characteristics. The two-step erasing scheme, where a channel erase cycle is added after the source erase operation, is found to reduce the gate current degradation and also to improve the cell's endurance characteristics.

  • VIPMOS, a Buried Local Injector for EPROMs

    A highly effective substrate hot electron injection EPROM device can be made using a buried injector, which operates in punch-through mode. The buried injector is formed by a local overlap of the N-well and P-well of a retrograde twin-well CMOS-process. As the VIPMOS-EPROM is compatible with VLSI-processing and the danger of latch-up doesn't exist, the VIPMOS-structure may be used in VLSI-applications. Due to an efficient electron supply mechanism as well as a high injection probability, programming rates of 1V/μs can be obtained.

  • Hot electron improvement in MOS RAM's based on epitaxial substrate

    None

  • A better understanding of substrate enhanced gate current in VLSI MOSFET's and flash cells. I. Phenomenological aspects

    This paper analyzes in depth the phenomenon of gate current enhancement upon application of a substrate voltage (|V/sub B/|) recently observed in deep submicron MOSFETs. The correlation between the gate (I/sub G/) and the substrate (I/sub B/) current is studied as a function of |V/sub B/|, and it is shown: (1) to provide an experimental signature of the onset of a new injection regime; and (2) to suggest a simple technique for separating the substrate enhanced gate current component from the conventional channel hot electron one. An empirical model of the new injection regime is assessed and the dependence of the model parameter on the lateral and vertical field is demonstrated. The sensitivity of the enhanced gate current to device design issues is also characterized. Different charge injection mechanisms compatible with the highlighted correlation between I/sub G/ and I/sub B/ are carefully analyzed in Part II.

  • Consistent gate and substrate current modeling based on energy transport and the lucky electron concept

    A numerical model for electron gate and substrate currents in n-channel silicon MOS devices is presented. The model accurately describes hot electron injection into the gate oxide triggered by substrate voltage, drain voltage, and substrate current over a large range of bias conditions and channel lengths. In all three cases the electrons with energies higher than the respective threshold energy are modeled identically. Differences due to different physical mechanisms involved in the three cases are taken into account by means of three different constant leading factors.<<ETX>>

  • A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection

    A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROM's. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown to be more than a hundred times shorter than the previous scheme. With the convergence operation performed near the ON-OFF transition region of the cells, the total drain current for all the converged cells is reduced and low power consumption is achieved.<<ETX>>

  • A better understanding of substrate enhanced gate current in VLSI MOSFETs and flash cells. II. Physical analysis

    For pt. I see ibid., vol. 46, no. 2 (Feb. 1999). In this work-different physical mechanisms that could lead to the direct proportionality between I/sub G/ and I/sub B/ as the signature of substrate enhanced electron injection (SEEI), are analyzed in detail. By means of experiments and simulations we substantiate the current interpretation of SEEI in terms of an impact ionization feedback process and attribute a quantitatively negligible role to both drain avalanche hot electron injection and substrate electrons generated by the photons emitted by channel hot electrons. These experiments reconcile the current explanation of SEEI with the well known phenomenon of photon assisted minority carrier injection in the substrate, whose presence is clearly detectable in our devices, but whose impact on the gate current is estimated to be orders of magnitude smaller than that of impact ionization feedback.

  • Substrate injection induced program disturb-a new reliability consideration for flash-EPROM arrays

    The development of high-density flash EPROMs is being directed towards scalability, sector erase, and 5-V-only operation. For the flash concepts that are utilizing channel hot electron injection for the programming, a new disturbance mechanism caused by substrate injection of thermally generated electrons is reported. This mechanism disturbs an erased call during programming cycles of other bits along the same bitline. The high-temperature programming requirement for flash EPROMs drastically enhances the disturbance through the strong increase in thermally generated electrons in the substrate. This program disturbance has the greatest impact on the wordline oriented sector erase memory architectures, through the increase in disturbance time.<<ETX>>

  • A novel mode of write operation utilizing avalanche-tunnel injection in MNOS memory transistor

    This paper describes a new mode of operation for a non-volatile read write random access memory, where a p-channel MNOS transistor is biased in a way different from the well-accepted direct tunneling mode of operation. The drain and source electrodes of the transistor are connected t9 the negative pulse voltage supply, while the gate and substrate are grounded. Hot electron injections into the insulator takes place from the avalanche plasma when the applied voltage exceeds the breakdown voltage of the drain and source junctions as in the case of FAMOS. Besides the simple avalanche injection, hot electron tunneling also takes place near the drain and source junctions and at the same time the electric field normal to the surface of the gate region under the avalanche breakdown condition causes the direct tunneling.



Standards related to Substrate hot electron injection

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IEEE Application Guide for Distributed Digital Control and Monitoring for Power Plants


IEEE Guide for Synthetic Fault Testing of AC High-Voltage Circuit Breakers Rated on a Symmetrical Current Basis


IEEE Standard for Broadband over Power Line Networks: Medium Access Control and Physical Layer Specifications

The project defines a standard for high-speed (>100 Mbps at the physical layer) communication devices via electric power lines, so-called broadband over power line (BPL) devices. This standard uses transmission frequencies below 100 MHz. It is usable by all classes of BPL devices, including BPL devices used for the first-mile/last-mile connection (<1500 m to the premise) to broadband services as ...


Standard for Safety Levels with Respect to Human Exposure to Radio Frequency Electromagnetic Fields, 3 kHz to 300 GHz - Amendment: Specifies Ceiling Limits for Induced and Contact Current, Clarifies Distinctions between Localized Exposure and Spatial Peak Power Density

This amendment specifies ceiling values for induced and contact current, clarifies the distinctions between “localized exposure” and “spatial peak power density,” and corrects other known technical and editorial errors.



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