Single event transient
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The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.
The conference will provide a forum for discussions and presentations of advancements inknowledge, new methods and technologies relevant to industrial electronics, along with their applications and future developments.
fusion engineering, physics and materials, plasma heating, vacuum technology, tritium processing, fueling, first walls, blankets and divertors
Meeting of academia and research professionals to discuss reliability challenges.
The annual IEEE SoutheastCon conferences promote all aspects of theories and applications of engineering disciplines. Sponsored by the IEEE Region-3 and IEEE Huntsville Section, this event will attract researchers, professionals, and students from the Southeastern region of the U.S. SoutheastCon 2019 will feature tutorial sessions, workshops, Technical Programs, and student Hardware, Software, Ethics, Paper, Web competitions.
The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...
Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...
2007 9th European Conference on Radiation and Its Effects on Components and Systems, 2007
IEEE Transactions on Nuclear Science, 2005
Angular dependence of proton-induced Multiple-Bit Upsets (MBUs) in a synchronous SRAM is reported. Experiments showed that the cross section of MBU depended on proton energy, incident direction, and physical arrangement of sensitive transistors in adjacent cells. Also analysis clarified that there was a special condition which MBU could be caused by a mechanism of Single- Event Upsets (SEUs), not by ...
2007 9th European Conference on Radiation and Its Effects on Components and Systems, 2007
2004 IEEE International Reliability Physics Symposium. Proceedings, 2004
This paper presents an efficient and accurate numerical analysis technique to simulate single event upsets (SEUs) in logic circuits. Experimental results that show the method is accurate to within 10% of the results obtained using SPICE are provided. The proposed method is used to study the ability of a CMOS gate to tolerate SEUs as a function of injected charge ...
2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, 2009
Evaluating the potential functional effects of soft errors (single or multiple bit-flips) in digital circuits becomes a critical design constraint. The usual approaches, based on fault injection techniques, suffer several limitations. New approaches, better suited to large circuits with complex workloads, are therefore suitable. An innovative approach was recently proposed, based on probabilistic testability analysis. This paper compares the presented ...
The Future of Consumer Robotics
An IEEE IPC Special Session with X. Chen from Nokia Bell Labs
Energy Efficient Single Flux Quantum Based Neuromorphic Computing - IEEE Rebooting Computing 2017
PES Scholarship Initiative Plus - Robert Thomas, Ph.D. Presentation
Neuromorphic computing with integrated photonics and superconductors - Jeffrey Shainline: 2016 International Conference on Rebooting Computing
A Comparison Between Single Purpose and Flexible Neuromorphic Processor Designs: IEEE Rebooting Computing 2017
Single Frame Super Resolution: Fuzzy Rule-Based and Gaussian Mixture Regression Approaches
IMS MicroApps: Single Chip LNA on 0.25um SOS for SKA Midband Receiver
Broadband IQ, Image Reject, and Single Sideband Mixers: MicroApps 2015 - Marki Microwave
ASC-2014 SQUIDs 50th Anniversary: 5 of 6 - Ronny Stolz - SQUIDs in Geophysics
Maker Faire 2008: Spectrum's Digital Clock Contest Winner
Single Die Broadband CMOS Power Amplifier and Tracker with 37% Overall Efficiency for TDD/FDD LTE Applications: RFIC Industry Forum
Approximate Dynamic Programming Methods A Unified Framework
Nanophotonic Devices for Quantum Information Processing: Optical Computing - Carsten Schuck at INC 2019
Multiobjective Quantum-inspired Evolutionary Algorithm and Preference-based Solution Selection Algorithm
A Wideband Single-PLL RF Receiver for Simultaneous Multi-Band and Multi-Channel Digital Car Radio Reception: RFIC Industry Showcase
Handling of a Single Object by Multiple Mobile Robots based on Caster-Like Dynamics
Single Crystal AlGaN Bulk Acoustic Wave Resonators on Silicon Substrates with High Electromechanical Coupling: RFIC Industry Showcase
IEEE IPC Special Session with Domanic Lavery of UCL
Angular dependence of proton-induced Multiple-Bit Upsets (MBUs) in a synchronous SRAM is reported. Experiments showed that the cross section of MBU depended on proton energy, incident direction, and physical arrangement of sensitive transistors in adjacent cells. Also analysis clarified that there was a special condition which MBU could be caused by a mechanism of Single- Event Upsets (SEUs), not by that of MBUs.
This paper presents an efficient and accurate numerical analysis technique to simulate single event upsets (SEUs) in logic circuits. Experimental results that show the method is accurate to within 10% of the results obtained using SPICE are provided. The proposed method is used to study the ability of a CMOS gate to tolerate SEUs as a function of injected charge and transistor sizing (aspect ratio W/L). A novel radiation hardening technique to calculate the minimum transistor size required to make a CMOS gate immune to SEUs is also presented. The results agree well with SPICE simulations, while allowing for very fast analysis. The technique can be easily integrated into design automation tools to harden sensitive portions of logic circuits.
Evaluating the potential functional effects of soft errors (single or multiple bit-flips) in digital circuits becomes a critical design constraint. The usual approaches, based on fault injection techniques, suffer several limitations. New approaches, better suited to large circuits with complex workloads, are therefore suitable. An innovative approach was recently proposed, based on probabilistic testability analysis. This paper compares the presented results with results obtained from extensive fault injection campaigns.
The systematic recording of single event upsets on TDRS-1 from 1984 to 1990 allows correlations to be drawn between those upsets and the space environment. Ground based neutron monitor data are used to illustrate the long-term relationship between galactic cosmic rays and TDRS-1 upsets. The short-term effects of energetic solar particles are illustrated with space environment data from GOES-7.<<ETX>>
Spare columns are often included in memories for the purpose of allowing for repair in the presence of defective cells or bit lines. In many cases, the repair process will not use all spare columns. This paper proposes an extremely low cost method to exploit these unused spare columns to improve the reliability of the memory by enhancing its existing error correcting code (ECC). Memories are generally protected with single-error-correcting, double- error-detecting (SEC-DED) codes using the minimum number of check bits. In the proposed method, unused spare columns are exploited to store additional check bits which can be used to reduce the miscorrection probability for triple errors in SEC-DED codes or non-adjacent double errors in single adjacent error correcting codes (SEC-DAEC) codes.
This work investigates the charge collection mechanisms occurring in heavy ion irradiated metal oxide semiconductor (MOS) devices. The parasitic bipolar effect, inherent to the structure of SOI transistors, is shown to exist in bulk NMOS transistors as well. We experimentally show that the drain junction of an OFF-state bulk MOS transistor collects more charge than an identical junction isolated from neighboring elements. In other words, the proximity of the source junction and the triggering of the bipolar-like structure are responsible of charge amplification. A higher current peak on the drain is observed, and this enhancement effect is high enough to invalidate usual charge collection models based only on funnel and diffusion transport. Thus, the proximity of other junctions has to be considered to improve charge collection model in bulk technologies.
This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high energy particles, alpha and neutrons in the atmosphere. For each of protections, the applicability, efficiency and implementation issues are discussed. Moreover, the area, the power and the protection capability of the methods are mentioned and compared with previous work. Based on the results of experiments and their analysis, one method is selected as best one. The selected method is much better than previous work e.g., duplication with comparison, triple modular redundancy which impose two and three area and power overheads, respectively.
Asynchronous circuits are often claimed as being an interesting alternative to design robust systems against faults. In this study, a method is proposed to model the behavior of quasi delay insensitive (QDI) asynchronous circuits in the presence of SEUs (memory bit flips). The circuits and the fault injection process are both described using this model. The method, based on symbolic simulation, consists of exploring all the reachable states in the presence of faults in order to draw up an exhaustive list of behaviors. A case study shows that this method enables us to verify some properties on the circuits. SEU resistance can be formally proven using this analysis.
his standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.