7,319 resources related to Silicon germanium
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.
All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation
The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
All aspects of optical guided-wave science, technology, and engineering in the areas of fiber and cable technologies; active and passive guided-wave componentry (light sources, detectors, repeaters, switches, fiber sensors, etc.); integrated optics and optoelectronics; systems and subsystems; new applications; and unique field trials.
IEEE Micro magazine presents high-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems. Topics include architecture, components, subassemblies, operating systems, application software, communications, fault tolerance, instrumentation, control equipment, and peripherals.
2008 33rd IEEE Photovoltaic Specialists Conference, 2008
Phase diagrams have been developed to guide very high frequency (vhf) plasma- enhanced chemical vapor deposition (PECVD) of intrinsic hydrogenated amorphous silicon (a-Si:H), amorphous silicon-germanium alloys (a-Si1-xGex:H), and nanocrystalline silicon (nc-Si:H) for use as the top, middle, and bottom cell i-layer components, respectively, of triple junction n-i-p solar cells. These phase diagrams have been used in conjunction with cross-sectional transmission ...
2013 1st International Conference on Artificial Intelligence, Modelling and Simulation, 2013
The Single and Dual Strained SiGe layer for Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET (VESIMOS) have been successfully analyzed in this paper. It is found that drain current for single (SC) and dual channel (DC) VESIMOS were increased sharply initially due to the presence of Germanium. Germanium has high impact ionization rates to ensure that the transition from ...
27th European Solid-State Device Research Conference, 1997
IEEE Transactions on Electron Devices, 2012
The floating-body effect and impact ionization generate excess holes that are amplified by the parasitic bipolar junction transistor (BJT) in silicon-on- insulator lateral double-diffused MOSFETs (SOI-LDMOS) that degrade the transistor performance. In this paper, a novel silicon germanium (SiGe) window LDMOS on SOI (SW-SOI) is reported where the buried oxide under the channel region becomes thinner and a SiGe window ...
2003 33rd European Microwave Conference, 2003
Design of Monolithic Silicon-Based Envelope-Tracking Power Amplifiers for Broadband Wireless Applications
From the Quantum Moore's Law toward Silicon Based Universal Quantum Computing - IEEE Rebooting Computing 2017
Silicon THz: an Opportunity for Innovation
IMS MicroApps: Silicon Technology Solutions for Wireless Front End Modules
Silicon Labs' Thunderboard Sense (SLTB001A): Mouser Engineering Bench Talk
An IEEE IPC Special Session with Alexander Spott of The Optoelectronics Research Group
IEEE Patent Presentation
Silicon Photonics: An IPC Keynote with Michal Lipson
Nanophotonic Devices for Quantum Information Processing: Optical Computing - Carsten Schuck at INC 2019
Single Crystal AlGaN Bulk Acoustic Wave Resonators on Silicon Substrates with High Electromechanical Coupling: RFIC Industry Showcase
Moving from Si to SiC from the End User’s Perspective - Muhammad Nawaz, APEC 2018
Origins of Silicon Valley - Paul Wesling - IEEE Sarnoff Symposium, 2019
Steep Slope Devices: Advanced Nanodevices - Nicolo Oliva at INC 2019
Chief Scientist Barbara De Salvo on How Leti is a Pioneer to Innovation - 2016 Women in Engineering Conference
ISSCC 2012 - Formal Opening
Transphorm: Redefining Energy Efficiency
Ready, Fire, Aim - Highlights of Hot Chips 20
The 6-Minute Memristor
KeyTalk with Ljubisa Stevanovic: From SiC MOSFET Devices to MW-scale Power Converters - APEC 2017
Phase diagrams have been developed to guide very high frequency (vhf) plasma- enhanced chemical vapor deposition (PECVD) of intrinsic hydrogenated amorphous silicon (a-Si:H), amorphous silicon-germanium alloys (a-Si1-xGex:H), and nanocrystalline silicon (nc-Si:H) for use as the top, middle, and bottom cell i-layer components, respectively, of triple junction n-i-p solar cells. These phase diagrams have been used in conjunction with cross-sectional transmission electron microscopy (XTEM) to identify nucleation and growth behavior in order to gain a better understanding of phase evolution. The substrates for phase diagram development by real time spectroscopic ellipsometry (RTSE) are crystalline Si wafers that have been over-deposited with either n-type a-Si:H for the top and middle cell amorphous i-layers, or n-type nc-Si:H for the bottom cell nanocrystalline i-layer. Identical n/i cell structures were co- deposited on textured (stainless steel)/Ag/ZnO, which serve as substrate/back- reflectors, in order to relate the RTSE-developed phase diagrams to the performance parameters of single-junction solar cells. This study has reaffirmed that the highest efficiencies for a-Si:H and a-Si1-xGex:H solar cells are obtained when the i-layers are prepared under previously-described maximal H2dilution conditions. The phase diagram for the bottom cell using a nc-Si:H n-layer reveals for the first time a bifurcation at a critical R value between mixed-toamorphous phase transitions [(a+nc) → a] at low R and mixed- to-single phase nanocrystalline transitions at high R [(a+nc) → nc]. The highest efficiency single-step nc-Si:H solar cell is obtained at minimal R while remaining on the nanocrystalline side of the identified bifurcation where suitable grain boundary passivation is assured.
The Single and Dual Strained SiGe layer for Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET (VESIMOS) have been successfully analyzed in this paper. It is found that drain current for single (SC) and dual channel (DC) VESIMOS were increased sharply initially due to the presence of Germanium. Germanium has high impact ionization rates to ensure that the transition from OFF state to ON state is abrupt. However, breakdown voltage of the SC device was decreased from B<sub>V</sub>=2.9V to 2.5V by increasing the composition of Ge from 10% to 30%. The same characteristics were found for DC VESIMOS where B<sub>V</sub>= 2V had decreased to 1.6V by varying the Ge composition. In short, the breakdown voltage which affected by the appearance of second SiGe channel and Ge composition was justified. Apart from that, with the presence of second SiGe channel, the switching speed and I<sub>ON</sub>/I<sub>OFF</sub> of the device were improved. It was found that the sub-threshold slope of SC and DC VESIMOS were inversely proportional to the breakdown voltage. Hence, DC VESIMOS can be promoted as extraordinary candidate for low power nanoelectronics device.
The floating-body effect and impact ionization generate excess holes that are amplified by the parasitic bipolar junction transistor (BJT) in silicon-on- insulator lateral double-diffused MOSFETs (SOI-LDMOS) that degrade the transistor performance. In this paper, a novel silicon germanium (SiGe) window LDMOS on SOI (SW-SOI) is reported where the buried oxide under the channel region becomes thinner and a SiGe window has been replaced in order to reduce the hole concentration in the channel and control the BJT effect significantly. The novel features of an SW-SOI are simulated and compared with a conventional LDMOS on SOI (C-SOI). In addition, reduced self-heating effects and higher breakdown voltage have been achieved as compared with the C-SOI. Hence, this paper illustrates the benefits of the high performance SW-SOI device over a conventional one and expands the application of SOI MOSFETs to high temperature.
The effects of degradation of the electronic properties of a-Si:H and a-(Si,Ge):H alloys on light soaking on the device physics of the a-Si and a-(Si,Ge) cells are examined. It is shown that both the decrease in mobility- lifetime products and the decrease in electric field in the middle of the device contribute to the rapid decrease in fill factor. To the authors propose using a novel graded bandgap scheme, where the grading in the bandgap is in the middle of the device. The feasibility of fabricating such devices is examined.<<ETX>>
SiGeC alloys are used to realize high performance compact integrated photonic devices, such as electro-optic modulators and photodetectors, on Silicon at near-IR wavelengths with performances that exceed those of conventional designs.
Advanced channel formation technologies called HEtero-layer-lift-off utilizing SiGe heteroepitaxy have been realized for fabricating ultrathin body (UTB) Ge- on-insulator (GeOI) structures. Insertion of SiGe etching stop layer was found to be effective for reducing GeOI body thickness (Tbody) fluctuation. Backside Si passivation for Ge/buried oxide interface has been verified to suppress backside Coulomb scattering and help to induce volume inversion effect. With improvement of backside interfacial quality and precise control of GeOI Tbody, primary carrier scattering factors in GeOI channel have been effectively reduced, resulting in significant improvement of hole mobility. High hole mobility of ~150 cm2/Vs in UTB GeOI pMOSFETs without strain technology has been demonstrated, which also outperformed Si universal mobility by 1.5 times even under Tbody of 9 nm. With low-thermal-budget process compatibility, UTB GeOI platform is very promising for future Ge large-scale integrated circuits devices used in monolithic 3-D integration scheme.
A 0.2 mum SiGe BiCMOS tuner for digital satellite audio radio applications was realized using a second-zero-IF dual conversion architecture with autonomous RF AGC and channel decoder controlled IF AGC. A single PLL drives both RF and IF mixers, resulting in a smaller die area and lower power dissipation. Providing a baseband I/Q output further reduces receiver's power due to a lower ADC and digital core operating frequency. SDARS tuner performance includes: 5dB noise figure, 55dB image rejection, -96 dBm input sensitivity, 100 mA current from a 3.3 V supply and 12 mm2 die area.
A straightforward modeling approach has been developed and used for the study of single- and tandem-pin solar cells made from amorphous silicon and its alloys with carbon and germanium before and after degradation. Experimental results on degradation of pure amorphous silicon cells (with SiC p-layer) can only be reproduced in the model by a rise of the bulk density of defect states in the i-layer. At the p-i and the i-n-interface, the defect density must be assumed to be high already before degradation.<<ETX>>
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