Silicon compiler

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A silicon compiler is a software system that takes a user's specifications and automatically generates an integrated circuit (IC). The process is sometimes referred to as hardware compilation. (Wikipedia.org)






Conferences related to Silicon compiler

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


IECON 2020 - 46th Annual Conference of the IEEE Industrial Electronics Society

IECON is focusing on industrial and manufacturing theory and applications of electronics, controls, communications, instrumentation and computational intelligence.


2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

ASP-DAC 2018 is the 23rd annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.


2018 31st IEEE International System-on-Chip Conference (SOCC)

System on Chip


2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

The IEEE Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems.


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Periodicals related to Silicon compiler

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Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Consumer Electronics, IEEE Transactions on

The design and manufacture of consumer electronics products, components, and related activities, particularly those used for entertainment, leisure, and educational purposes


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Most published Xplore authors for Silicon compiler

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Xplore Articles related to Silicon compiler

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Educating future chip designers

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1987

The evolution of analog and digital integrated circuits from small elements to complex systems is clearly documented in the past issues of the DIGEST. Improvements in technology and CAD, raise some vital questions about the areas that future chip designers need to understand and the venue for this training. The answers depend strongly on the techniques and tools available for ...


Layout Generation for Multipliers in VLSI-Digital Signal Processing

ESSCIRC '84: Tenth European Solid-State Circuits Conference, 1984

This paper presents a parameterization concept for the automatic layout generation of multipliers in digital signal processing. Based on a hierarchical cell design methodology the layout of parameterized two's complement bit-parallel multipliers can automatically be generated according to any desired wordwidth of multiplicand and multiplier. Additionally the product can be rounded or truncated to either the longer or smaller wordwidth ...


A design synthesis system for DSP algorithms based on an optimal multiprocessor scheduler

Proceedings of 26th Southeastern Symposium on System Theory, 1994

This paper describes a design synthesis system which can generate a complete circuit specification efficiently for a given DSP algorithm based on an optimal multiprocessor scheduler. The design synthesis system is composed of two parts: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph (FSFG) as input, and generates an optimal synchronous multiprocessor schedule. Then the ...


ASIC design system for radiation environments

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, 1991

A complete radiation hardened ASIC design system, under development by a three company team is described. The compiler approach design system, with radiation hardness tunable library cells, allows the designer to concentrate on the circuit design rather than the details of hardness affecting geometry layout. The designer must be aware of the hardness requirements and the limitations of the available ...


PROXIMA: an integrated Prolog machine

ESSCIRC '90: Sixteenth European Solid-State Circuits Conference, 1990

The paper describes the basic design methodology and the technological aspects involved in the integration of a high performance Prolog machine on silicon. The need of an efficient Prolog engine arises from the A.I. applications requiring great symbolic computation power. Currently available Prolog machines are implemented using a large number of boards. As a consequence they are expensive, cumbersome and ...


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Educational Resources on Silicon compiler

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IEEE-USA E-Books

  • Educating future chip designers

    The evolution of analog and digital integrated circuits from small elements to complex systems is clearly documented in the past issues of the DIGEST. Improvements in technology and CAD, raise some vital questions about the areas that future chip designers need to understand and the venue for this training. The answers depend strongly on the techniques and tools available for the chip designer: whether CAD will provide powerful compilers, freeing the designer to focus on system issues, or whether the demands of performance tuning debugging and normal design will force the designer to understand circuits. To discuss these issues, panelists will review opinions on the relative importance of the spectrum from device physics to system architecture.

  • Layout Generation for Multipliers in VLSI-Digital Signal Processing

    This paper presents a parameterization concept for the automatic layout generation of multipliers in digital signal processing. Based on a hierarchical cell design methodology the layout of parameterized two's complement bit-parallel multipliers can automatically be generated according to any desired wordwidth of multiplicand and multiplier. Additionally the product can be rounded or truncated to either the longer or smaller wordwidth of the both input vectors.

  • A design synthesis system for DSP algorithms based on an optimal multiprocessor scheduler

    This paper describes a design synthesis system which can generate a complete circuit specification efficiently for a given DSP algorithm based on an optimal multiprocessor scheduler. The design synthesis system is composed of two parts: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph (FSFG) as input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the design synthesis process with an example of a second order Gray-Markel lattice filter.<<ETX>>

  • ASIC design system for radiation environments

    A complete radiation hardened ASIC design system, under development by a three company team is described. The compiler approach design system, with radiation hardness tunable library cells, allows the designer to concentrate on the circuit design rather than the details of hardness affecting geometry layout. The designer must be aware of the hardness requirements and the limitations of the available compilable process technologies, but is not burdened with the transistor level design techniques to achieve the hardness desired.<<ETX>>

  • PROXIMA: an integrated Prolog machine

    The paper describes the basic design methodology and the technological aspects involved in the integration of a high performance Prolog machine on silicon. The need of an efficient Prolog engine arises from the A.I. applications requiring great symbolic computation power. Currently available Prolog machines are implemented using a large number of boards. As a consequence they are expensive, cumbersome and have not yet achieved industrial standards. The described processor, PROXIMA, is a VLSI Prolog engine prototype suited to be added on a commercial workstation. The project has been carried out as a cooperative effort of SGS-Thomson Microelectronics and the Politecnico di Torino.

  • State assignment based on the reduced dependency theory and recent experimental results

    A state assignment method is described. The first step of this method recognizes predictive minimization situations in the control flow graph. It is based on the partition pair theory and privileges the cube collapsing in the next state and output equations with regard to factorization. The second step uses a powerful intersecting face embedding theory in the Boolean lattice. This approach has been implemented by software in the ASYL system, and tested on official as well as industrial examples. The gain in silicon area, critical path, and routing factor with respect to random assignment appears to be the best presently known.<<ETX>>

  • A silicon compiler for fault-tolerant ROMs

    This paper describes a new CAD tool, FTROM-Fault-Tolerant ROM-compiler, for synthesizing fault-tolerant ROM modules with flexible, user-specified geometry and CMOS design-rule parameters. It employs a novel fault-tolerant design approach that produces negligible access delay penalty and silicon area overhead. FTROM reduces the design turnaround time and the BIST and BISR circuitry incorporated eliminate the high cost of external testing of commodity ROMs. Such circuits are also very useful for on-chip ROM macrocells used in high-density microprocessors and ASICs, since the I/O pins of such macrocells are extremely difficult to control and observe.

  • Bridging high-level slqvihesis to RTL technology libraries

    None

  • A VHDL based design environment for VLSI circuits

    Describes a design environment to model and simulate digital circuits described in VHDL (VHSIC Hardware Description Language). The simulator presented can accept behavioral and data-flow style descriptions. The simulator consists of two primary sections: a front end of the simulator, called an analyzer, and a back-end, called the simulation executive. The analyzer checks for the static errors in the VHDL input description. The analyzer consists of a lexical analyzer, a syntax analyzer, and a semantic analyzer. The lexical analyzer eliminates all the white spaces from the input description; the syntax analyzer checks for VHDL syntax; and the semantic analyzer performs type checking. The simulation executive is directly implemented through the semantic action parts of the lexical analyzer. The simulator's front-end sections, the scanner and the parser, have been implemented using the automated compiler construction tools LEX and YACC. The results of execution in the test program indicated that the simulator works correctly.<<ETX>>

  • ASIC design and analysis using the system design synthesis tool: four case studies

    An analysis, tradeoff, and design tool for ASICs that allows an engineer to consider and develop ASICs at a personal computer is discussed. Specific examples include missile guidance systems and CCD image processing. Each project took five days or less to complete, including the final output steps on the Genesil silicon compiler.<<ETX>>



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