Conferences related to Sequential diagnosis

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2023 Annual International Conference of the IEEE Engineering in Medicine & Biology Conference (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted full papers will be peer reviewed. Accepted high quality papers will be presented in oral and poster sessions,will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE.


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.


ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

The ICASSP meeting is the world's largest and most comprehensive technical conference focused on signal processing and its applications. The conference will feature world-class speakers, tutorials, exhibits, and over 50 lecture and poster sessions.


IECON 2020 - 46th Annual Conference of the IEEE Industrial Electronics Society

IECON is focusing on industrial and manufacturing theory and applications of electronics, controls, communications, instrumentation and computational intelligence.


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Periodicals related to Sequential diagnosis

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Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Computational Biology and Bioinformatics, IEEE/ACM Transactions on

Specific topics of interest include, but are not limited to, sequence analysis, comparison and alignment methods; motif, gene and signal recognition; molecular evolution; phylogenetics and phylogenomics; determination or prediction of the structure of RNA and Protein in two and three dimensions; DNA twisting and folding; gene expression and gene regulatory networks; deduction of metabolic pathways; micro-array design and analysis; proteomics; ...


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


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Most published Xplore authors for Sequential diagnosis

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Xplore Articles related to Sequential diagnosis

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A parallel built-in diagnostic scheme for multiple embedded memories

Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004., 2004

Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis ...


Good processor identification in two-dimensional grids

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), 1999

We examine the problem of identifying good processors in self-testing two- dimensional grid systems. The grids have boundaries (not wrap-around) and degree 8. Our diagnostic objective is to identify at least one fault-free processor. From this, at feast one faulty processor could be identified and it would be possible to sequentially diagnose the system by repeated repair. We establish an ...


Characterization and design of sequentially t-diagnosable systems

[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers, 1989

In the system-level diagnosis area, F.P. Preparata, G. Metze, and R.T. Chien (1967) first presented a formal graph-theoretic model and introduced the concept of sequentially t-diagnosable systems. A system S is called sequentially t-diagnosable if, given any complete collection of test results, at least one faulty unit in S can be identified, provided the number of faulty units does not ...


Three-valued system diagnosis and parallel recovery

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic, 1988

A generalized three-valued diagnostic model is proposed. A description is given of t1/t1/2-diagnosability with a parallel recovery strategy. The results show clearly that t-1/t-1/2-diagnosis with parallel recovery can effectively shorten the period of recovery time from faults and improves availability of a class of fault-tolerant computer systems, as compared with t-fault diagnosis under the same structural constraint.<<ETX>>


Upper bounds for the degree of sequential diagnosability

IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242), 1998

It is known that an n-dimensional grid with N vertices, an N-vertex hypercube, and a k-ary tree with N vertices are sequentially /spl Omega/(N/sup n/(n+1)/)-, /spl Omega/(N log log N/log N)-, and /spl Omega/(/spl radic/N/k)-diagnosable, respectively. This paper shows that they are sequentially O(N/sup n/(n+1)/)-, O(N log log N//spl radic/log N)-, and o(/spl radic/kN)-diagnosable, respectively.


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Educational Resources on Sequential diagnosis

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IEEE.tv Videos

Multiple Sensor Fault Detection and Isolation in Complex Distributed Dynamical Systems
Photo Verification Technology for Radiology Images - Srini Tridandapani - IEEE EMBS at NIH, 2019
ASC-2014 SQUIDs 50th Anniversary: 4 of 6 - Keiji Enpuku
VisualDx Augmented Intelligence Project - Arthur Papier - IEEE EMBS at NIH, 2019
Engineering in Medicine and Biology: Segment 3
Panel: Unmet Needs in HIV/AIDS & TB Diagnosis & Management - IEEE EMBS at NIH, 2019
Learning Method of the SIC Fuzzy Inference Model - Genki Ohashi - ICRC San Mateo, 2019
Molecular Diagnostics for STIs - Gary Schoolnik - IEEE EMBS at NIH, 2019
Machine Ethics - Proceedings of the IEEE Webinar
Unmet Needs in the Diagnosis and Management of TB - Richard Chaisson - IEEE EMBS at NIH, 2019
Implantable Wireless Medical Devices and Systems
Yulun Wang accepts the IEEE Medal for Innovations in Healthcare Technology - Honors Ceremony 2017
Thoughts on “POC” in the Digital Era - Keynote Robert Califf - IEEE EMBS at NIH, 2019
How Facial Analysis Technology Can Help Children with Genetic Disorders - IEEE Region 4 Technical Presentation
Fragility of Interconnected Cyber-Physical Systems - Marios M. Polycarpou - WCCI 2016
Unlocking Diagnostic Access in Local Health - Catharina Boehme - IEEE EMBS at NIH, 2019
Charles A. Mistretta accepts the IEEE Medal for Innovations in Healthcare Technology - Honors Ceremony 2016
Fuzzy and Soft Methods for Multi-Criteria Decision Making - Ronald R Yager - WCCI 2016
Developing POC Technology for Existing Health Care System - Sally McFall - IEEE EMBS at NIH, 2019
Fireside Chat: Key Opinion Leaders on Pre-Symptomatic Illness Detection - IEEE EMBS at NIH, 2019

IEEE-USA E-Books

  • A parallel built-in diagnostic scheme for multiple embedded memories

    Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis (PBISD) scheme was developed to work with our existing memory optimization and reconfiguration (MORE) system, which configures small memory cores into the large one specified by the user, subject to the power and geometry constraints. With PBISD and MORE, memory test and diagnosis can be done in a much shorter time, and the whole system provides a good balance among test time, test power, and test hardware overhead. Experimental results show that, when compared with a conventional BISD scheme, the diagnosis time for a case with four memory cores is only 25%. Moreover, the area overhead is only 49%, as only one test pattern generator is required.

  • Good processor identification in two-dimensional grids

    We examine the problem of identifying good processors in self-testing two- dimensional grid systems. The grids have boundaries (not wrap-around) and degree 8. Our diagnostic objective is to identify at least one fault-free processor. From this, at feast one faulty processor could be identified and it would be possible to sequentially diagnose the system by repeated repair. We establish an upper bound on the worst case maximum number of faults while still being able to meet the diagnostic goal with an ideal diagnosis algorithm. A straightforward ideal diagnosis algorithm would have exponential complexity and would involve 16 parallel rounds of processor testing. We give a test schedule with at most 6 parallel rounds of testing. This test schedule tolerates asymptotically as many faults as an ideal algorithm (by a constant factor). The new test schedule will also work for grids with degree 4, which have inferior diagnostic potential.

  • Characterization and design of sequentially t-diagnosable systems

    In the system-level diagnosis area, F.P. Preparata, G. Metze, and R.T. Chien (1967) first presented a formal graph-theoretic model and introduced the concept of sequentially t-diagnosable systems. A system S is called sequentially t-diagnosable if, given any complete collection of test results, at least one faulty unit in S can be identified, provided the number of faulty units does not exceed t. However, until very recently, developing a characterization theorem of sequentially t-diagnosable systems for the PMC model was still an important, open problem. The authors resolve this problem by presenting the first complete characterization. A canonical class of systems, D/sub 1,k/ systems, is discussed, and a valuable result on the sequential t-diagnosability is obtained.<<ETX>>

  • Three-valued system diagnosis and parallel recovery

    A generalized three-valued diagnostic model is proposed. A description is given of t1/t1/2-diagnosability with a parallel recovery strategy. The results show clearly that t-1/t-1/2-diagnosis with parallel recovery can effectively shorten the period of recovery time from faults and improves availability of a class of fault-tolerant computer systems, as compared with t-fault diagnosis under the same structural constraint.<<ETX>>

  • Upper bounds for the degree of sequential diagnosability

    It is known that an n-dimensional grid with N vertices, an N-vertex hypercube, and a k-ary tree with N vertices are sequentially /spl Omega/(N/sup n/(n+1)/)-, /spl Omega/(N log log N/log N)-, and /spl Omega/(/spl radic/N/k)-diagnosable, respectively. This paper shows that they are sequentially O(N/sup n/(n+1)/)-, O(N log log N//spl radic/log N)-, and o(/spl radic/kN)-diagnosable, respectively.

  • Query ranking strategies in probabilistic expert systems

    The number of features are quite high in many fields. For instance, the number of symptoms are around thousands in probabilistic medical expert systems. Since it is not practical to query all the symptoms to reach the diagnosis, query choice becomes important. In this work, 3 query ranking strategies in probabilistic expert systems are proposed and their performances on synthetic data are evaluated.

  • Sequential diagnosis for BC graphs

    Sequential diagnosis is a more practical approach to fault diagnosis of multicomputer networks, when the diagnosability of one-step diagnosis is bounded by the minimum vertex degree in its interconnection graph. The BC graphs (bijective connection graphs) are a class of newly introduced interconnection topologies, which include hypercubes, twisted cubes, Möbius cubes and crossed cubes, etc. This paper describes a generalized sequential diagnosis algorithm for BC graphs under PMC model. It is shown that BC graphs of n dimensions are Ω(N log log N/log N)-diagnosable, where N = 2n is the total number of nodes of a BC graph.

  • t-Fault t/2-step sequentially diagnosable systems

    Fault diagnosis is considered for systems comprising n units u<inf>0</inf>, u<inf>1</inf>,...,u<inf>n-1</inf>in which u<inf>i</inf>tests u<inf>i+1</inf>and u<inf>i+2</inf>. A necessary and sufficient condition for the diagnosability of t faults in t/2 or t/2 + 1/2 steps is stated, the condition taking the form of an inequality relating n and t.

  • On sequential diagnosability of 2-dimensional meshes and tori

    This paper considers sequential diagnosability of multiprocessor systems under the PMC model. In this model, the processors can test each other along communication links in the multiprocessor systems. A system is said to be sequentially t-diagnosable if at least one faulty processors can be identified from any set of test results provided that the number of faulty processors does not exceed t. The degree of sequential diagnosability of a multiprocessor system is maximum t such that the system is sequentially t-diagnosable. It is known that the degree of sequential diagnosability of the system modeled by a 2-dimensional square grid or torus with N vertices is Theta(N<sup>2/3</sup>). This paper generalizes this result, and is proved that that of a 2-dimentional ltimesm grid or torus is O(min{N<sup>2/3</sup>, radiclN}), where N = l times m and l les m.

  • Sequential diagnosability of t-diagnosable systems

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