Conferences related to Sequential circuits

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2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation


2020 IEEE/PES Transmission and Distribution Conference and Exposition (T&D)

Bi-Annual IEEE PES T&D conference. Largest T&D conference in North America.


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Periodicals related to Sequential circuits

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Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


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Most published Xplore authors for Sequential circuits

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Xplore Articles related to Sequential circuits

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A single-chip sequential logic element

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1978

A field-programmable logic sequencer, containing, on one chip, all of the circuitry required to implement an 11MHz synchronous sequential-state machine, will be covered. Nichrome fuse link technology has been used to afford direct entry of state transitions.


Session 4B - Sequential circuit optimization

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., 2005

None


Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking

Eighth IEEE International High-Level Design Validation and Test Workshop, 2003

Full sequential equivalence checking by state space traversal has been shown to be unpractical for large designs. To address state space explosion new approaches have been proposed that exploit structural characteristics of a design and make use of multiple analysis engines (e.g. BDDs, Simulation, SAT) to transform the sequential equivalence checking problem into a combinational equivalence checking problem. While these ...


Embedded system design with FPGA using HDL (lessons learned and pitfalls to be avoided)

2005 IEEE International Conference on Microelectronic Systems Education (MSE'05), 2005

This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short courses in industry. The courses have concentrated on logic synthesis targeting CPLD and FPGA. All the courses had a major laboratory component where students could use simulation tools to test their design using test ...


Computer-aided-design platform for sequential systems

Proceedings IEEE SOUTHEASTCON '97. 'Engineering the New Century', 1997

In this paper, we describe a computer-aided-design (CAD) platform that lets the users conceptually design, simulate and test a state machine. This platform allows the users to graphically specify synchronous sequential systems expressed as algorithmic state machine (ASM) charts and then produces logic circuit diagrams with actual components specification. Using a graphic editor, ASM charts are created by placing and ...


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Educational Resources on Sequential circuits

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IEEE-USA E-Books

  • A single-chip sequential logic element

    A field-programmable logic sequencer, containing, on one chip, all of the circuitry required to implement an 11MHz synchronous sequential-state machine, will be covered. Nichrome fuse link technology has been used to afford direct entry of state transitions.

  • Session 4B - Sequential circuit optimization

    None

  • Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking

    Full sequential equivalence checking by state space traversal has been shown to be unpractical for large designs. To address state space explosion new approaches have been proposed that exploit structural characteristics of a design and make use of multiple analysis engines (e.g. BDDs, Simulation, SAT) to transform the sequential equivalence checking problem into a combinational equivalence checking problem. While these approaches, based on induction techniques, have been successful in general, they are not able to reach proof of equivalence in presence of complex transformations between the reference design and its implementation. One of these transformations is redundant Flip- Flops (FFs) removal. FFs may be removed by redundancy removal, or don't care optimization techniques applied by synthesis tools. Consequently, some FFs in the reference design may have no equivalent FFs in the implementation net- list. Latest researches in this area have proposed specific solutions for particular cases. Matching in the presence of redundant constant input FFs has been addressed and identification of sequential redundancy is performed. This paper presents an indepth study of some possible causes of unmatched FFs due to redundancy removal, and proposes a generic approach to achieve prove of equivalence in presence of redundant FFs. Our approach is independent from specific synthesis transformations. It is able to achieve matching in presence of complex redundancies, and is able to perform formal equivalence checking in presence of don't cares. The experimental results show a significant improvement in the matching rates of FFs when compared to industrial equivalence checking tools. This higher matching is directly translated to a higher success rate in proving equivalency.

  • Embedded system design with FPGA using HDL (lessons learned and pitfalls to be avoided)

    This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short courses in industry. The courses have concentrated on logic synthesis targeting CPLD and FPGA. All the courses had a major laboratory component where students could use simulation tools to test their design using test benches and also synthesis tools to synthesize, implement, and download the configuration bit-stream to evaluation boards. The paper concentrates on some of the problems that students encounter when they are trying to design their digital systems using HDL. In addition to the conceptual issues with using a language to describe hardware behavior, the newer higher capacity devices provide additional challenges as more functions, including embedded processors, are added to the device.

  • Computer-aided-design platform for sequential systems

    In this paper, we describe a computer-aided-design (CAD) platform that lets the users conceptually design, simulate and test a state machine. This platform allows the users to graphically specify synchronous sequential systems expressed as algorithmic state machine (ASM) charts and then produces logic circuit diagrams with actual components specification. Using a graphic editor, ASM charts are created by placing and combining objects on the screen such as states, transitions, inputs, outputs, and text. The graphic editor provides a complete object-oriented drawing environment with standard drawing tools as well as specific functions tailored for ASM chart's creation. Once an ASM chart is validated, the CAD platform relieves the designer of the many intermediate tedious steps required for the final minimal logic circuit realization of the synchronous system defined.

  • Sequential Circuit Test Generator (STG) benchmark results

    The authors report on the results of running a version of the Sequential Circuit Test Generator (STG3) on the ISCAS-89 sequential circuit benchmarks. First, they present a brief history of STG and briefly describe the algorithms used. They then describe the conditions under which the experiments were run and give the benchmark results. No particular problems were encountered when running STG3 on the benchmark circuits, except for those circuits with many untestable faults. STG3 determines that faults are undetectable fairly quickly, taking only 0.98 s on a totally untestable circuit. The major problem with the circuits considered untestable was in initializing the circuit state.<<ETX>>

  • Automated ILA design for VLSI synchronous state machines

    An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This architecture realizes a sequential circuit by replicating simple basic modules. With an ILA architecture, a sequential machine can be built into a very regular form automatically generated by a computer program with a single type of ILA module. The simplicity and programmability of the ILA architecture significantly reduce the design task in all stages of VLSI implementation, including logic design, circuit design, artwork generation, and verification. A software algorithm in the C language hs been developed and tested to generate 1- mu m CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.<<ETX>>

  • A Sequential Circuit Partitioning Algorithm for Dynamically Reconfigurable FPGAs

    In this paper, we present a sequential circuit partitioning algorithm to minimize the number of registers for dynamically reconfigurable FPGAs. The algorithm is performed on our specific graph model and divided into two phases: 1) the labeling phase and 2) the minimizing cost phase. We first use as soon as possible and as late as possible algorithms to assign nodes so that the precedence constraints are satisfied. Then, some nodes are adjusted or replicated according to several proposed methods to minimize the number of registers. Experimental results demonstrate the effectives of our algorithms.

  • Robust testing for stuck-at faults

    This paper proposes a generalization of robust tests with respect to assumptions about fault models and circuit models. The specific case of d-robust tests for single stuck-at faults is studied. These tests maintain their validity in the presence of macro-delay faults. A macro-delay of size n means that the delay of all combinational paths can be in the range [O,nT] where T is the clock period. We give a simple method of duplicating a test vector n times to produce a d-robust test for a stuck-at fault in a combinational circuit. We further implement a more complex algorithm to derive d-robust tests for stuck-at faults in sequential circuits.

  • Recovery from Transition Errors in Sequential Circuits

    We consider the impact of one-cycle transient faults on the state behavior of sequential circuits. The resultant errors are broadly classified into non- critical output errors and critical (state) transition errors. We also study the time required for recovery (self-healing) from transition errors under random input sequences, and present some experimental data for benchmark circuits.



Standards related to Sequential circuits

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(Replaced) IEEE Standard VHDL Language Reference Manual

his standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.



Jobs related to Sequential circuits

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