Conferences related to Semiconductor-insulator interfaces

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2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Magnetic Conference (INTERMAG)

INTERMAG is the premier conference on all aspects of applied magnetism and provides a range of oral and poster presentations, invited talks and symposia, a tutorial session, and exhibits reviewing the latest developments in magnetism.


2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


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Periodicals related to Semiconductor-insulator interfaces

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Dielectrics and Electrical Insulation, IEEE Transactions on

Electrical insulation common to the design and construction of components and equipment for use in electric and electronic circuits and distribution systems at all frequencies.


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


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Most published Xplore authors for Semiconductor-insulator interfaces

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Xplore Articles related to Semiconductor-insulator interfaces

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Thickness determination of poly-Si/poly-oxide/poly-Si/SiO/sub 2//Si structure by ellipsometer

Electronics Letters, 1993

An ellipsometry measurement method is proposed to measure poly-Si/poly-oxide /poly-Si/SiO/sub 2//Si structure. The thickness of each layer in this structure can be easily obtained by a conventional ellipsometry measurement. The measured result is consistent with that of cross-sectional TEM.<<ETX>>


Rapid thermal annealing and performance of Al2O3/GaN metal-oxide-semiconductor structures

2006 International Conference on Advanced Semiconductor Devices and Microsystems, 2006

In this paper we investigate growth of Al<sub>2</sub>O<sub>3</sub> and performance of Al<sub>2</sub>O<sub>3</sub>/GaN MOS structures using O<sub>2</sub>, Ar and NH<sub>3</sub> pre-treatment of GaN surface. Rapid thermal annealing (RTA) after the growth is also tested. Current-voltage (I-V) and thermal activation energy measurements were used for characterization of MOS and reference Ni/GaN Schottky contact structures. From the I-V characteristics, reduction of the leakage ...


Low temperature low pressure MOCVD Al/sub x/Ga/sub 1-x/As layer grown as a dielectric for GaAs MIS devices

Electronics Letters, 1995

An oxygen doped Al/sub x/Ga/sub 1-x/As layer is demonstrated as a dielectric for GaAs MIS structures. This layer is MOCVD grown at 550/spl deg/C with an operating pressure of 10 torr. By keeping the aluminium content low, it is possible to obtain a dielectric with relatively high resistivity and very good interface quality.


A New Step In The Electrical Characterisation Of Silicon-Insulator Interfaces

2006 Conference on Optoelectronic and Microelectronic Materials and Devices, 2006

The principle of charge pumping (CP), the most widely used semiconductor- insulator interface traps electrical characterisation method, is recalled first. Then, a rigorous model proposed recently for this technique is summarised. A CP technique proposed a few years ago is also presented. Assuming tunnelling for the capture of carriers, the trap depth concentration profiles, from the Si-SiO<sub>2</sub> interface towards the ...


Direct measurements of trap density in a SiGe/Si hetero-interface and correlation between the trap density and low-frequency noise in SiGe-channel pMOSFETs

IEEE Transactions on Electron Devices, 2003

The interface trap density in a SiGe/Si heterostructure has been successfully measured for the first time using a low-temperature charge pumping technique in a SiGe-channel pMOSFET, avoiding interference from the interface traps between the gate oxide and the semiconductor surface. Moreover, low-frequency noise in the SiGe pMOSFETs has been measured to investigate any correlation with the trap density observed at ...


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Educational Resources on Semiconductor-insulator interfaces

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IEEE-USA E-Books

  • Thickness determination of poly-Si/poly-oxide/poly-Si/SiO/sub 2//Si structure by ellipsometer

    An ellipsometry measurement method is proposed to measure poly-Si/poly-oxide /poly-Si/SiO/sub 2//Si structure. The thickness of each layer in this structure can be easily obtained by a conventional ellipsometry measurement. The measured result is consistent with that of cross-sectional TEM.<<ETX>>

  • Rapid thermal annealing and performance of Al2O3/GaN metal-oxide-semiconductor structures

    In this paper we investigate growth of Al<sub>2</sub>O<sub>3</sub> and performance of Al<sub>2</sub>O<sub>3</sub>/GaN MOS structures using O<sub>2</sub>, Ar and NH<sub>3</sub> pre-treatment of GaN surface. Rapid thermal annealing (RTA) after the growth is also tested. Current-voltage (I-V) and thermal activation energy measurements were used for characterization of MOS and reference Ni/GaN Schottky contact structures. From the I-V characteristics, reduction of the leakage current was observed in MOS structures compared with the Schottky contacts for all types of processing, from three to five orders of magnitude in the reverse bias. Barrier height at the semiconductor-insulator interface (Phi<sub>S-1</sub>), which is responsible for the reduction of the forward bias leakage was extracted from the thermal I-V measurements. Values of Phi<sub>S-1</sub> was found to be ~1.6eV for O<sub>2</sub> and ~2.5eV for Ar treated samples and these samples show substantial leakage reduction in both senses. On the other hand I-V performance of the MOS structures with the NH<sub>3 </sub> pretreatment resemble Schottky contact diode-like characteristic

  • Low temperature low pressure MOCVD Al/sub x/Ga/sub 1-x/As layer grown as a dielectric for GaAs MIS devices

    An oxygen doped Al/sub x/Ga/sub 1-x/As layer is demonstrated as a dielectric for GaAs MIS structures. This layer is MOCVD grown at 550/spl deg/C with an operating pressure of 10 torr. By keeping the aluminium content low, it is possible to obtain a dielectric with relatively high resistivity and very good interface quality.

  • A New Step In The Electrical Characterisation Of Silicon-Insulator Interfaces

    The principle of charge pumping (CP), the most widely used semiconductor- insulator interface traps electrical characterisation method, is recalled first. Then, a rigorous model proposed recently for this technique is summarised. A CP technique proposed a few years ago is also presented. Assuming tunnelling for the capture of carriers, the trap depth concentration profiles, from the Si-SiO<sub>2</sub> interface towards the oxide bulk extraction can be extracted. Combining these two approaches, i.e. accounting for the trap depth distribution in the rigorous CP model allows for the first time to simulate CP curves in all experimental conditions. The curves obtained are compared with experimental results. It is shown that information on the trap properties can be obtained from the differences between both curve types. The generalised CP model enables to know the energy and depth region of the oxide probed in all the experimental conditions. A new spectroscopic CP technique is also presented. Based on the frequency dependence of the CP curves, it allows to evidence and to study the traps at the Si-SiO<sub>2</sub> interface. The traps in the oxide can also be studied independently. The simulations exhibit again the same features as the experimental curves do. Again, trap characteristics can be obtained from the differences between both curve types.

  • Direct measurements of trap density in a SiGe/Si hetero-interface and correlation between the trap density and low-frequency noise in SiGe-channel pMOSFETs

    The interface trap density in a SiGe/Si heterostructure has been successfully measured for the first time using a low-temperature charge pumping technique in a SiGe-channel pMOSFET, avoiding interference from the interface traps between the gate oxide and the semiconductor surface. Moreover, low-frequency noise in the SiGe pMOSFETs has been measured to investigate any correlation with the trap density observed at the SiGe/Si hetero-interface. A good correlation was obtained between the measured interface trap density in the heterostructure and the low-frequency noise level in the current flowing in the SiGe-channel.

  • A versatile, SOI BiCMOS technology with complementary lateral BJT's

    A silicon-on-insulator, fully-complementary BiCMOS process has been developed for realizing high-performance circuit operation in the sub-3.3 V power supply regime. Complementary, double-diffused lateral BJTs and fully-overlapped, asymmetrical DDD MOSFETs have been successfully integrated in a 10-mask process by utilizing the process simplifications that are unique to thin-film SOI substrates. The BJTs exhibit the highest lateral current gains reported to date, with h/sub fe/=120 and 225 for the NPN and PNP, respectively. NPN f/sub t/=4.5 GHz was achieved, and f/sub t/>20 GHz is possible with an improved layout. The MOSFETs demonstrate excellent short-channel behavior down to L/sub eff/=0.18 mu m, with T/sub ox/=10 nm. The p+ gate, SOI PMOS device exhibits superior I/sub dsat/ and g/sub msat/. A record propagation delay of 12 ps/stage at V/sub dd/=5 V and 300 K was obtained for the CMOS ring oscillators fabricated in this technology. This demonstrates the performance achievable with a deep-submicron SOI process.<<ETX>>

  • Dependence of radiation induced damage on gate oxide thickness in MOS capacitors with ultrathin gate oxides

    The effect of scaling down gate oxide thickness on radiation induced damage in MOS capacitors with sub-10 nm gate oxides is reported. The trend of reduction in radiation induced positive charge and interface state generation is observed to continue for these ultrathin gate oxides. Results show that neutral trap generation due to radiation exposure is negligible in sub-10 nm gate oxides.<<ETX>>

  • Stress-induced current in thin silicon dioxide films

    Low-field current following Fowler-Nordheim stress of thin gate oxides is studied. The conduction mechanism is attributed to trap-assisted tunneling of electrons. For oxides thicker than 100 AA, this stress-induced current is observed to decay as traps are filled without significant tunneling out of traps. In thinner oxides, steady-state current flows when there is an equilibrium between trap filling and emptying processes. This model is observed to be consistent with stress-induced current behavior in a wide range of oxide thicknesses (60 AA to 130 AA) and process technologies.<<ETX>>

  • A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

    A mechanism is proposed for reconciling an observed large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET. The dopant in the source-drain extension is assumed to segregate to the Si/SiO/sub 2/ interface by a reversible reaction. It then diffuses along the interface into the channel region where the dopant is able to return to the bulk Si. By this means a shallow sliver of p-type dopant is formed which protrudes laterally from the source-drain extension into the channel. Simulations with this model are found to match measured PFET device parameters where other assumptions fail,.

  • Heavy oxynitridation technology for forming highly reliable flash-type EEPROM tunnel oxide films

    For the first time, it is demonstrated that in flash-type EEPROMs, the endurance properties are dramatically improved by heavy oxynitridation (RTONO) of the tunnel oxide. The layer composition evaluated by SIMS measurement indicates that large amounts of N atoms (>10/sup 20/ atom/cm/sup 3/) pile up at the SiO/sub 2/-Si interface, and are distributed in the bulk SiO/sub 2/. In addition, the RTONO film reduces the number of hydrogen atoms, which are the origin of electron traps. This oxynitridation causes a decrease of both electron and hole traps in the tunnel oxide, resulting in an improvement of the threshold voltage narrowing.<<ETX>>



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