Conferences related to Semiconductor epitaxial layers

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2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation


2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems & Eurosensors XXXIII (TRANSDUCERS & EUROSENSORS XXXIII)

The world's premiere conference in MEMS sensors, actuators and integrated micro and nano systems welcomes you to attend this four-day event showcasing major technological, scientific and commercial breakthroughs in mechanical, optical, chemical and biological devices and systems using micro and nanotechnology.The major areas of activity in the development of Transducers solicited and expected at this conference include but are not limited to: Bio, Medical, Chemical, and Micro Total Analysis Systems Fabrication and Packaging Mechanical and Physical Sensors Materials and Characterization Design, Simulation and Theory Actuators Optical MEMS RF MEMS Nanotechnology Energy and Power


2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe)

Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies


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Periodicals related to Semiconductor epitaxial layers

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Lightwave Technology, Journal of

All aspects of optical guided-wave science, technology, and engineering in the areas of fiber and cable technologies; active and passive guided-wave componentry (light sources, detectors, repeaters, switches, fiber sensors, etc.); integrated optics and optoelectronics; systems and subsystems; new applications; and unique field trials.


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Most published Xplore authors for Semiconductor epitaxial layers

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Xplore Articles related to Semiconductor epitaxial layers

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IEE Colloquium on 'GaAs on Si' (Digest No.47)

IEE Colloquium on GaAs on Si, 1988

None


Measurement of epitaxial layer resistivity using MOS capacitance method

Proceedings of the IEEE, 1967

Metal-oxide-semiconductor (MOS) capacitance-voltage measurements are used to determine the epitaxial layer resistivity. This method can be used to characterize epitaxial layers without removing the oxide present on the as- received wafers. The results are compared with that obtained by diode- capacitance technique and point contact method.


Application of radiation enhanced diffusion to microwave transistor fabrication

1971 International Electron Devices Meeting, 1971

The use of preferential Radiation Enhanced Diffusion (RED) of impurities from an n<sup>+</sup>silicon substrate doped with antimony to an n<sup>-</sup>silicon epitaxial layer by proton irradiation followed by the phosphorus atom implantation into an n<sup>-</sup>epitaxial layer, again followed by the proton irradiation, has been successfully applied to microwave transistor fabrication. This increases the power gain by reducing collector capacitance, C<inf>c</inf>, while ...


Fabrication process and device characteristics of sidewall base contact structure transistor using two-step oxidation of sidewall surface

IEEE Transactions on Electron Devices, 1988

A novel bipolar process technology for sidewall base contact structure (SICOS) transistors and the effects of sidewall base contact width on device characteristics are described. The sidewall window width can be precisely controlled by utilizing two-step oxidation of a sidewall surface (TOSS). Such a surface is made by using two-step etching of a silicon epitaxial layer and through the formation ...


Lift-off of silicon epitaxial layers for solar cell applications

Conference Record of the Twenty Sixth IEEE Photovoltaic Specialists Conference - 1997, 1997

We have developed a technique which allows the fabrication of single crystalline layers of silicon of arbitrary size and shape and with a thickness ranging from less than 50 to greater than 100 /spl mu/m. The films are grown by liquid phase epitaxy (LPE) on single crystal silicon substrates which have been patterned with a suitable masking layer material such ...


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Educational Resources on Semiconductor epitaxial layers

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IEEE-USA E-Books

  • IEE Colloquium on 'GaAs on Si' (Digest No.47)

    None

  • Measurement of epitaxial layer resistivity using MOS capacitance method

    Metal-oxide-semiconductor (MOS) capacitance-voltage measurements are used to determine the epitaxial layer resistivity. This method can be used to characterize epitaxial layers without removing the oxide present on the as- received wafers. The results are compared with that obtained by diode- capacitance technique and point contact method.

  • Application of radiation enhanced diffusion to microwave transistor fabrication

    The use of preferential Radiation Enhanced Diffusion (RED) of impurities from an n<sup>+</sup>silicon substrate doped with antimony to an n<sup>-</sup>silicon epitaxial layer by proton irradiation followed by the phosphorus atom implantation into an n<sup>-</sup>epitaxial layer, again followed by the proton irradiation, has been successfully applied to microwave transistor fabrication. This increases the power gain by reducing collector capacitance, C<inf>c</inf>, while maintaining high f<inf>T</inf>, which is difficult to realize by conventional means.

  • Fabrication process and device characteristics of sidewall base contact structure transistor using two-step oxidation of sidewall surface

    A novel bipolar process technology for sidewall base contact structure (SICOS) transistors and the effects of sidewall base contact width on device characteristics are described. The sidewall window width can be precisely controlled by utilizing two-step oxidation of a sidewall surface (TOSS). Such a surface is made by using two-step etching of a silicon epitaxial layer and through the formation of two sidewall SiO/sub 2/ and two sidewall Si/sub 3/N/sub 4/ layers. The key point in the TOSS processes is the optimization of the two sidewall Si/sub 3/N/sub 4/ thicknesses. This is necessary to prevent the extension of the bird's beak to the first sidewall SiO/sub 2/ so that the sidewall window can be selectively opened and to prevent the generation of defects. By applying the TOSS processes to a SICOS transistor, the sidewall window width can be controlled as desired. As a result, the dependences of breakdown voltage, junction capacitance, cutoff frequency, and switching speed on the sidewall window width are clarified.<<ETX>>

  • Lift-off of silicon epitaxial layers for solar cell applications

    We have developed a technique which allows the fabrication of single crystalline layers of silicon of arbitrary size and shape and with a thickness ranging from less than 50 to greater than 100 /spl mu/m. The films are grown by liquid phase epitaxy (LPE) on single crystal silicon substrates which have been patterned with a suitable masking layer material such as SiO/sub 2/. Detachment of the layers proceeds by etching through the regions where the epitaxial layer is attached to the substrate. In contrast to the technique utilised for the epitaxial lift-off of III-V compounds, this approach does not require an extremely selective etchant which etches a buffer layer while not attacking the epitaxial layer. The substrate can be re-used many times.

  • High-speed photoluminescence mapping of III-V epitaxial layers for light emitting diodes

    Photoluminescence (PL) mapping has been developed at the Hewlett-Packard Optoelectronics Division as a non-destructive characterization tool for the evaluation of III-V semiconductor epitaxial layer uniformity in light emitting diode (LED) devices. It has been used as an aid in the development of new epitaxial growth processes and as a quality screening method for cost reduction in a high volume manufacturing line. The design and characterization of a high-speed full wafer PL mapping system based on an optical multichannel analyzer is discussed. This system allows simultaneous mapping of peak wavelength, PL power and power uniformity at several hundred points per wafer in under 10 minutes. Three examples are given of the application of this tool in a combined development/manufacturing environment. In the development of a new MOCVD AlInGaP epitaxial growth process it is being used to evaluate epi reactor designs, gas flow dynamics and the effect of substrate rotation on uniformity. In a well-established production VPE GaAsP epi process PL mapping is routinely used to get rapid feedback on the effect of minor process variations made to improve uniformity. Finally, as a manufacturing tool in high volume production lines, PL mapping can be used to reduce product costs by screening epi into LED product lines with different uniformity requirements.

  • High-resistance thick silicon epitaxial layers

    The development and introduction of powerful high-voltage diodes and transistors, p-i-n diodes, photodiodes, avalanche diodes and other devices require silicon epitaxial layers with high resistance and large thickness, smooth surfaces and a considerable extent of crystallographic perfection, i.e. a minimal number of structural defects. CVD appears to be the most suitable technology for obtaining such layers.

  • Modulation-doped double-barrier quantum well infrared detectors for photovoltaic operation in 3-5 μm

    With the aim of combining the mid-infrared detection with the photovoltaic (PV) mode operation, we present in this work a series of modulation-doped (MD) quantum well infrared photodetectors (QWIPs) based on AlGaAs-AlAs-GaAs, that exhibit a remarkable responsivity at zero bias (0.05 A/W at 25 K). Since the PV signal is strongly dependent on the symmetry of the potential profile, we have varied the dopant location in the AlGaAs barriers. The responsivity and detectivity of the MD devices, in particular for the MD detector with the dopant at the substrate side AlGaAs barrier, seem to be higher to those of a well-doped sample of nominally the same structure, also considered for comparison. Self-consistent calculations for the potential profile of the MD devices are compared with experiment.

  • Sidewall epitaxial piezoresistor process for in-plane sensing applications

    We report, a novel, selective epitaxial fabrication method to form piezoresistors on the sidewalls of microstructures for in-plane sensing applications. We have fabricated and characterized cantilevered force sensors with lateral piezoresistors. Their sensitivity was found to be 2-7 times more sensitive than most ion-implanted cantilevers we have made with equivalent dopant concentration. In addition, we have characterized noise and electrical characteristics and the effect of trench dimension on deposition rate.

  • Si-homoepitaxy by electron cyclotron resonance CVD

    Low-temperature homoepitaxy of silicon has been achieved at T=450/spl deg/C by using electron cyclotron resonance CVD (2.45 GHz, up to 1.5 kW). H/sub 2/ and H/sub 2//Ar were used as excitation gases and either SiH/sub 4/ or mixtures of SiH/sub 4/ with PH/sub 3//H/sub 2/ or B/sub 2/H/sub 6//H/sub 2/ served as process gas. The epitaxial layers were grown with a thickness of up to 3 /spl mu/m at a rate of up to 25 nm/min. Highly phosphorus-doped epitaxial layers were used as emitters in 2/spl times/2 cm/sup 2/ solar cell structures on p-type FZ- and SILSO-wafers as base material. These cells had AM1.5 efficiencies of up to 15% and 11%, respectively. The results suggest that recombination at the base-emitter interface is a limiting factor.



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