Hardware Software Co-design
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
ISIE focuses on advancements in knowledge, new methods, and technologies relevant to industrial electronics, along with their applications and future developments.
APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics
The 2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC 2020) will be held in Metro Toronto Convention Centre (MTCC), Toronto, Ontario, Canada. SMC 2020 is the flagship conference of the IEEE Systems, Man, and Cybernetics Society. It provides an international forum for researchers and practitioners to report most recent innovations and developments, summarize state-of-the-art, and exchange ideas and advances in all aspects of systems science and engineering, human machine systems, and cybernetics. Advances in these fields have increasing importance in the creation of intelligent environments involving technologies interacting with humans to provide an enriching experience and thereby improve quality of life. Papers related to the conference theme are solicited, including theories, methodologies, and emerging applications. Contributions to theory and practice, including but not limited to the following technical areas, are invited.
The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.
Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97, 1997
The increasing complexity of hardware/software systems is handled effectively by hardware/software codesign methods. However, the debugging of hardware/software systems is still a very troublesome process. This is mainly due to the limited accessibility to the internals of embedded hardware/software systems. Debugging is also hindered by the nature of the design errors encountered during hardware/software debugging. We present a structured design-for-debug ...
2009 IEEE 10th International Conference on Computer-Aided Industrial Design & Conceptual Design, 2009
A system-on-chip hardware/software co-design platform was presented based on model driven-based design method. After the overall architecture of platform was described, four design levels and three mapping processes were introduced. Some key techniques were explained in detail, such as hardware/software partitioning algorithm based on genetic algorithm & constraint task scheduling, UML profile for SystemC model and template-based model-to-text transform method. ...
2013 International Symposium on Intelligent Signal Processing and Communication Systems, 2013
In this paper, we propose a hardware-software co-design solution for a real- time noise cancelling algorithm using spectral subtraction algorithm. The hardware and software are partitioned based on the logic size and the speed performance. Considering the speed, hanning windowing filter and 64-point I/FFT are implemented in a dedicated hardware modules. Due to design complexity and size optimization, noise spectral ...
2007 11th International Conference on Computer Supported Cooperative Work in Design, 2007
Nowadays it is widely adopted by reconfigurable computing system developers to obtain significant performance improvements through converting computational intensive codes from software to hardware. To program for such systems with hardware accelerators included, the programmers have to know the details of hardware accelerators, and control the configurations of hardware accelerators as well as communications between software and hardware parts. This ...
2010 International Conference on Measuring Technology and Mechatronics Automation, 2010
This paper presents the implementation of a face detection algorithm on FPGA for an eye mouse control system. An improved algorithm of skin color module and binary image projection is used to ensure real-time detection. The system is based on a hardware/software co-design, which consists of a dedicated hardware accelerator that solves the parts of the algorithm with higher computational ...
A Unified Hardware/Software Co-Design Framework for Neuromorphic Computing Devices and Applications - IEEE Rebooting Computing 2017
Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning - Dejan Milojicic - ICRC 2018
Micro-Apps 2013: Creating and Analyzing Multi-Emitter Environment Test Signals with COTS Equipment
Co-Design of Algorithms & Hardware for DNNs - Vivienne Sze - LPIRC 2019
50 Fog Design Tips in 50 Minutes - Chuck Byers, Fog World Congress 2017
Robotics History: Narratives and Networks Oral Histories: Brian Gerkey
Technologies for 5G course, Part 4 - IEEE Smart Tech Workshop
Technologies for 5G course, Part 3 - IEEE Smart Tech Workshop
Nebbiolo Technologies Pitch: Fog Tank - Fog World Congress
Technologies for 5G course, Part 2 - IEEE Smart Tech Workshop
Q&A with Dejan Milojicic: IEEE Rebooting Computing Podcast, Episode 9
Technologies for 5G course, Part 1 - IEEE Smart Tech Workshop
Bug Labs: How an Open Source Gadget Works
Welcome: Low Power Image Recognition Challenge
Development of Quantum Annealing Technology at D-Wave Systems - 2018 IEEE Industry Summit on the Future of Computing
Interview with Takao Nishitani - IEEE Donald O. Pederson Award in Solid-State Circuits Co-Recipient 2017
Control of a Fully-Actuated Airship for Satellite Emulation
An In-Depth Look At Baidu's (BIDU) Artificial Intelligence Aspirations - ICRC San Mateo, 2019
A Principled Way to Use Frameworks in Architecture Design
The increasing complexity of hardware/software systems is handled effectively by hardware/software codesign methods. However, the debugging of hardware/software systems is still a very troublesome process. This is mainly due to the limited accessibility to the internals of embedded hardware/software systems. Debugging is also hindered by the nature of the design errors encountered during hardware/software debugging. We present a structured design-for-debug strategy to address the problems of hardware/software debugging. Our design-for-debug strategy is an integral part of hardware/software codesign. Furthermore, we re-use the hardware design-for- test-facilities to reduce the overhead costs of design-for-debug. Two examples are provided to illustrate our design-for-debug strategy.
A system-on-chip hardware/software co-design platform was presented based on model driven-based design method. After the overall architecture of platform was described, four design levels and three mapping processes were introduced. Some key techniques were explained in detail, such as hardware/software partitioning algorithm based on genetic algorithm & constraint task scheduling, UML profile for SystemC model and template-based model-to-text transform method. Take design of a MIL-STD-1553B bus system with PCI interface for example, working flow of system-on-chip hardware/software co-design on the platform was provided.
In this paper, we propose a hardware-software co-design solution for a real- time noise cancelling algorithm using spectral subtraction algorithm. The hardware and software are partitioned based on the logic size and the speed performance. Considering the speed, hanning windowing filter and 64-point I/FFT are implemented in a dedicated hardware modules. Due to design complexity and size optimization, noise spectral estimator and spectral subtraction algorithm are implemented in a host processor using software. We utilize SPARC-V8 based LEON3 processor as a host processor. In order to increase the speed of software processing, we use FPU as a floating point arithmetic co-processor. Besides, we also propose a dedicated DMA architecture design to support high speed AMBA based burst transfer to communicate between dedicated hardware modules and host processor. The proposed system has latency less than 1 ms (<; 4ms) and 12 ms processing delay. The MSE is only 0.0089%. Therefore, the system can work in real-time and many clock cycles are still available for future algorithm improvement.
Nowadays it is widely adopted by reconfigurable computing system developers to obtain significant performance improvements through converting computational intensive codes from software to hardware. To program for such systems with hardware accelerators included, the programmers have to know the details of hardware accelerators, and control the configurations of hardware accelerators as well as communications between software and hardware parts. This state-of art programming style is not efficient for system development. In this paper, a transparent hardware-software co-design framework for reconfigurable computing system is proposed. It allows the programmers to access the hardware accelerators in the same way as calling software functions, leaving the configuration and communication issues to underlying operating system and assistant hardware control logic. Dynamic function calling is also supported in this model to utilize the dynamic reconfiguration ability of the modern programmable devices for reducing the requirement of hardware resources, hence increasing the efficiency of the whole system.
This paper presents the implementation of a face detection algorithm on FPGA for an eye mouse control system. An improved algorithm of skin color module and binary image projection is used to ensure real-time detection. The system is based on a hardware/software co-design, which consists of a dedicated hardware accelerator that solves the parts of the algorithm with higher computational cost and an embedded microprocessor that manages the control process and executes the rest of the algorithm. Several optimization methods have been accomplished to enhance performance. The system has been implemented on an Altera Cyclone II FPGA using a Nios embedded soft-core processor and it is benchmarked against a software implementation. It is demonstrated that a 640×480 pixel image can be analyzed in 96 ms with a clock frequency of 100 MHz.
This work presents a method to characterize heterogeneous hardware/software systems mapped onto Configurable SoCs (CSoC) in situ, where in situ implies that the CSoC being characterized is also the final target platform. The result of our proposed method is a trade-off curve of different configurations with unique area vs. performance characteristics, each of which uses a different micro-architecture for the accelerators. Our work has been prototyped on a DE1-SoC FPGA board containing a Cyclone V SoC FPGA with two ARM cores and reconfigurable fabric onto which the complete trade-off curves with dominating designs for each BIP are mapped. A fast heuristic method is proposed, which compared to an exhaustive search method, leading to the optimal solution, is slightly worse while on average 15.2× faster, showing that it can lead to very good results quickly. The proposed method is also compared to a simulation-based offline method. In situ characterization is able to speed up the exploration by on average 25.6×, while being more accurate.
Blokus Duo is an abstract strategy game for two players. In this paper, we describe our FPGA implementation of Blokus Duo player for ICFPT2014 design contest, which is the revised version of the previous design for ICPFT2013 design contest. Our design consists of hardware logic part and software part using soft IP processor. The hardware logic part calculates evaluation value of the board status which is a heavy task for the software part. Our implementation uses recursive Alpha-Beta pruning and iteration deepening algorithm by the software part, which are complex to implement as the hardware logic circuit. The current version of our implementation on Xilinx Artix7 can run at 142MHz. The hardware logic part evaluates about 90,000 nodes in one second at the beginning of the game.
In this paper, a SystemC-based hardware/software co-design methodology for embedded image processing system is presented. With the development of the IC process, traditional design methodologies cannot meet the requirement of complex digital image processing systems. Hardware/software co-design is the new solution for designing embedded system. SystemC is promoted by the Open SystemC Initiative, which provides a well-defined set of C++ classes to accurately describe hardware; C++ can be chosen to describe both hardware and software throughout the whole design flow to support hardware/software co- design. SystemC can provide co-design platform for an embedded image processing system.
In this paper, we present a strategy and an FPGA implementation of a Connect6 player submitted to the FPT 2011 Design Competition. Connect6 is a two-player strategy board game. The winner of the game is the player who first gets six pieces of his color in a connected horizontal, vertical or diagonal line. We assign a strategic value to each potential move depending on the current board configuration. Our approach uses a minimal amount of situation dependent game logic in order to take full advantage of the available compute resources and parallelism. The FPGA implementation of this strategy always wins against the software opponent provided for the competition. Additionally, our implementation wins on average against different software AIs from , as long as no sophisticated game-tree search is performed by the software.
In this study, a computationally efficient method for echo detection and pulse compression based on ellipse fitting on the time-frequency representation of the signal is investigated. The algorithm successively estimates the chirplet parameters to decompose convoluted signals into a linear combination of chirp components. Analytical results show that the algorithm is efficient and successful in signal representation. For the real-time application, an embedded implementation of the ellipse fitting is implemented on Xilinx Vitex-5 FPGA platform. Based on the system constraints and the efficiency of estimations, the performances of different algorithm implementation schemes have been examined. The developed system-on-chip hardware/software co-design successfully demonstrates robustness in the chirplet decomposition of experimental signals.
This standard defines SystemC®1 as an ANSI standard C++ class library for system and hardware design.
Branch Head for Software Research and Development - CIPHER
Georgia Tech Research Institute (GTRI)