Conferences related to Hardware Emulation

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2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)

Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 18th International Conference on Industrial Informatics (INDIN)

INDIN focuses on recent developments, deployments, technology trends, and research results in Industrial Informatics-related fields from both industry and academia


2020 IEEE 29th International Symposium on Industrial Electronics (ISIE)

ISIE focuses on advancements in knowledge, new methods, and technologies relevant to industrial electronics, along with their applications and future developments.


2020 IEEE Applied Power Electronics Conference and Exposition (APEC)

APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics


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Periodicals related to Hardware Emulation

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems Magazine, IEEE


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Most published Xplore authors for Hardware Emulation

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Xplore Articles related to Hardware Emulation

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Fast prototyping of memory models in VHDL for hardware emulation

Proceedings Seventh IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype, 1996

In this paper, we present a methodology whereby the whole synthesis and prototyping cycle can be speeded up simply by extending the acceptable VHDL subset to include hitherto unsynthesisable constructs. VHDL elaboration transformations as well as some compiler optimisation techniques can be performed to ensure that the VHDL model is still acceptable by commercial synthesis tools. The advantages of this ...


Hardware emulation of IoT devices and verification of application behavior

2017 23rd Asia-Pacific Conference on Communications (APCC), 2017

In recent years, the Internet of Things (IoT) systems have been studied and discussed actively. The performance evaluation of IoT systems using hardware emulation is an important topic in Research and development (R&D), because it is prohibitive in terms of resources to use real devices as traffic sources for a large system evaluation of the IoT network. This study proposes ...


Reprogrammable hardware emulation for ASICs makes through design verification practical

Digest of Papers. COMPCON Spring 89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, 1989

The author argues that the current simulation-based product development methodologies have an intrinsic limitation that makes thorough ASIC (application-specific integrated circuits) design verification impractical at the system level. A description is given of technology called reprogrammable hardware emulation which, combined with simulation-based technologies, results in vastly more effective design verification approach. The author concludes that it is inevitable that reprogrammable ...


Cost Effective Partial Scan for Hardware Emulation

2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016

FPGA-based hardware emulation platform runs significantly faster than software simulation for verifying complex circuit designs. However, the controllability and observability of circuit internal signals mapped onto FPGAs are restricted due to the limited chip pins. Scan chain-based technique is effective in providing full-chip controllability and observability, at the cost of large area overhead, especially for FPGAs. Therefore, partial scan has ...


A solution for hardware emulation of non volatile memory macrocells

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003

More and more system verification makes use of hardware emulation techniques that allow a speed up in simulation performance of up to a thousand times. Typically, a design is composed of several parts, most of them available as RTL code, others, mainly memories, only as behavioral models. In this scenario, coemulation is necessary to verify the heterogeneous system descriptions, but ...


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Educational Resources on Hardware Emulation

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IEEE.tv Videos

Towards Higher Scalability of Quantum Hardware Emulation - Naveed Mahmud - ICRC 2018
Parallel Quantum Computing Emulation - Brian La Cour - ICRC 2018
Control of a Fully-Actuated Airship for Satellite Emulation
IEEE Entrepreneurship @ The 2017 AlphaLab Gear Hardware Cup International Finals
FPGA demonstrator of a Programmable ML Inference Accelerator - Martin Foltin - ICRC San Mateo, 2019
The EU Human Brain Project - A Systematic Path from Data to Synthesis
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
Co-Design of Algorithms & Hardware for DNNs - Vivienne Sze - LPIRC 2019
The 2018 AlphaLab Gear Hardware Cup International Finals
CES 2009: One OS Per Hard Drive
Cafe: Cloud Appliances for Enterprises
Bug Labs: How an Open Source Gadget Works
A Unified Hardware/Software Co-Design Framework for Neuromorphic Computing Devices and Applications - IEEE Rebooting Computing 2017
Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning - Dejan Milojicic - ICRC 2018
IEEE Entrepreneurship @ #HWCup2017: Rubitection
The Era of AI Hardware - 2018 IEEE Industry Summit on the Future of Computing
Hardware Detection in Implantable Media Devices Using Adiabatic Computing - S. Dinesh Kumar - ICRC 2018
New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks - Naveen Kumar Macha - ICRC 2018
IEEE Entrepreneurship @ #HWCup2017: PlayDate
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017

IEEE-USA E-Books

  • Fast prototyping of memory models in VHDL for hardware emulation

    In this paper, we present a methodology whereby the whole synthesis and prototyping cycle can be speeded up simply by extending the acceptable VHDL subset to include hitherto unsynthesisable constructs. VHDL elaboration transformations as well as some compiler optimisation techniques can be performed to ensure that the VHDL model is still acceptable by commercial synthesis tools. The advantages of this methodology are shown using a real industrial application: the development of a generic VHDL memory model for fast system reconfiguration in a hardware emulation environment.

  • Hardware emulation of IoT devices and verification of application behavior

    In recent years, the Internet of Things (IoT) systems have been studied and discussed actively. The performance evaluation of IoT systems using hardware emulation is an important topic in Research and development (R&D), because it is prohibitive in terms of resources to use real devices as traffic sources for a large system evaluation of the IoT network. This study proposes an IoT device with traffic generating functions as a hardware emulation of traffic source in an IoT network. The specifications and implementation of the IoT device are presented. Furthermore, the study also proposes application cases for the proposed device in an Intelligent Transport System (ITS).

  • Reprogrammable hardware emulation for ASICs makes through design verification practical

    The author argues that the current simulation-based product development methodologies have an intrinsic limitation that makes thorough ASIC (application-specific integrated circuits) design verification impractical at the system level. A description is given of technology called reprogrammable hardware emulation which, combined with simulation-based technologies, results in vastly more effective design verification approach. The author concludes that it is inevitable that reprogrammable hardware emulation will eventually be incorporated into the design-verification methodologies of all companies making a major commitment to the use of ASICs.<<ETX>>

  • Cost Effective Partial Scan for Hardware Emulation

    FPGA-based hardware emulation platform runs significantly faster than software simulation for verifying complex circuit designs. However, the controllability and observability of circuit internal signals mapped onto FPGAs are restricted due to the limited chip pins. Scan chain-based technique is effective in providing full-chip controllability and observability, at the cost of large area overhead, especially for FPGAs. Therefore, partial scan has been proposed as an alternative way to improve the controllability and observability while reducing the area cost. However, the optimized partial scan solution with the minimum number of scan flip-flops is not always found. This paper formulates the classical balanced structure partial scan procedure in one step as an integer linear programming problem, leading to the optimized partial scan solution. In addition, partially used logic resources in FPGAs are exploited to implement the extra logic required by the scan chain, to further reduce the area cost. Experimental results show that our partial scan approach can reduce the area overhead by 78.6% and 16.6% compared to the full scan and the existing partial scan approach.

  • A solution for hardware emulation of non volatile memory macrocells

    More and more system verification makes use of hardware emulation techniques that allow a speed up in simulation performance of up to a thousand times. Typically, a design is composed of several parts, most of them available as RTL code, others, mainly memories, only as behavioral models. In this scenario, coemulation is necessary to verify the heterogeneous system descriptions, but this way most of the advantage of hardware emulation is lost. This paper presents a solution for modeling the analog array of a non volatile memory based on a VHDL synthesizable description. The presented approach relies on static RAMs and ROMs for which emulation models are assumed to be available. The adoption of a synthesizable model for the analog block makes possible the mapping of the entire design on the emulator thus exploiting its performance at full speed for efficient simulation sessions.

  • Fast development of source-level debugging system using hardware emulation

    We describe the co-development of a processor and its source-level debugging system using an emulation-based validation technology including hardware emulation, not simulation, Since a source-level debugging system is essential to develop an application system and it takes a long time to validate the functionality of the source-level debugging system, we have adopted hardware emulation for a fast validation and system development. Using this methodology, we were able to validate the source-level debugging system successfully before the chip fabrication.

  • Hardware emulation of VLSI designs

    A commercially available hardware emulation system and its expected capabilities are described, and results of an evaluation using an existing VLSI chip are reviewed. Based on this experience, the potential of the emulation system in ASIC design is assessed and areas of improvement are suggested. A forecast is also given of possible evolution of hardware emulation.<<ETX>>

  • Introducing hardware emulation in the ECE curriculum

    This paper describes a collaborative effort between Mentor Graphics and Portland State University to introduce hardware emulation into the undergraduate and graduate electrical and computer engineering curriculum. We detail several parallel approaches that address a need for both broad exposure to the concepts of hardware emulation and more in-depth experience with transaction-based verification.

  • The Architecture, Design, and Operation of a Virtual Network Hardware Emulation (VNHE) System

    This paper presents an overview of the architecture, design, and operation of a virtual network hardware emulation system. The primary motivation for creating the system was to allow operating system development engineers to create virtual network based hardware devices, which allows the developers to create support software for the devices. The system also allows test engineers to test the devices virtually before the devices are physically manufactured and available. The virtual network hardware emulation system consists of seven primary software components, such as a WLan Virtual Miniport component, which simulate the behavior of their physical counterparts. The system is designed in a modular way which allows a wide range of network based hardware devices to be virtualized and tested.

  • Design verification based on hardware emulation

    The fast evolution of advanced integrated circuits which inevitably provides competitive products with improved functions and performance, has also forced the design verification process to become the bottleneck in today's design methodologies. We describe in this paper our experiences with the use of hardware emulation to boost the verification process.



Standards related to Hardware Emulation

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