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2021 IEEE Photovoltaic Specialists Conference (PVSC)
Photovoltaic materials, devices, systems and related science and technology
ICC 2021 - IEEE International Conference on Communications
IEEE ICC is one of the two flagship IEEE conferences in the field of communications; Montreal is to host this conference in 2021. Each annual IEEE ICC conference typically attracts approximately 1,500-2,000 attendees, and will present over 1,000 research works over its duration. As well as being an opportunity to share pioneering research ideas and developments, the conference is also an excellent networking and publicity event, giving the opportunity for businesses and clients to link together, and presenting the scope for companies to publicize themselves and their products among the leaders of communications industries from all over the world.
IEEE Global Communications Conference (GLOBECOM) is one of the IEEE Communications Society’s two flagship conferences dedicated to driving innovation in nearly every aspect of communications. Each year, more than 2,900 scientific researchers and their management submit proposals for program sessions to be held at the annual conference. After extensive peer review, the best of the proposals are selected for the conference program, which includes technical papers, tutorials, workshops and industry sessions designed specifically to advance technologies, systems and infrastructure that are continuing to reshape the world and provide all users with access to an unprecedented spectrum of high-speed, seamless and cost-effective global telecommunications services.
IEEE INFOCOM solicits research papers describing significant and innovative researchcontributions to the field of computer and data communication networks. We invite submissionson a wide range of research topics, spanning both theoretical and systems research.
The conference is the primary forum for cross-industry and multidisciplinary research in automation. Its goal is to provide a broad coverage and dissemination of foundational research in automation among researchers, academics, and practitioners.
The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...
Broadcast technology, including devices, equipment, techniques, and systems related to broadcast technology, including the production, distribution, transmission, and propagation aspects.
Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...
Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)
Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999
In this paper, we present a novel scheduling algorithm targeted toward minimizing the average execution time of control-flow intensive behavioral descriptions. Our algorithm uses a control/data flow graph model, which preserves the parallelism inherent in the application. It explores previously unexplored regions of the solution space by its ability to overlap the schedules of independent iterative constructs, whose bodies share ...
2011 International Conference on E-Business and E-Government (ICEE), 2011
In this paper, a high efficient dynamic scheduling algorithm is developed to schedule a set of multi-thread on realtime multiprocessor systems. The algorithm divides two grades schedule. The one-grade-schedule inserts the new thread into thread-queue of thread-queue matrix according to the restriction rules and insertion rules, the two-grade-schedule places some threads chose from thread matrix into two-grade-windows, and then assigns ...
2007 Chinese Control Conference, 2007
For scheduling messages in networked control system (NCS), the characters of messages in NCS are analyzed firstly in this paper. The message models are given and the relationship of messages is studied. Non pre-emptive EDF (earliest deadline first) is selected for scheduling messages and the method for realizing the scheduling algorithm is presented based on token control. The schedulability of ...
IEEE Transactions on Computers, 2008
With the advent of powerful network processors (NPs) in the market, many computation-intensive tasks such as routing table look-up, classification, IPSec, and multimedia transcoding can now be accomplished more easily in a router. An NP consists of a number of on-chip processors to carry out packet level parallel processing operations. Ensuring good load balancing among the processors increases throughput. However, ...
IEEE Transactions on Parallel and Distributed Systems, 1999
In the area of parallelizing compilers, considerable research has been carried out on data dependency analysis, parallelism extraction, as well as program and data partitioning. However, designing a practical, low complexity scheduling algorithm without sacrificing performance remains a challenging problem. A variety of heuristics have been proposed to generate efficient solutions but they take prohibitively long execution times for moderate ...
Challenging the stigma surrounding the role of women in technology, a journey from combinatorial optimization to IBM
Towards Higher Scalability of Quantum Hardware Emulation - Naveed Mahmud - ICRC 2018
Dynamic Selection of Evolutionary Algorithm Operators Based on Online Learning and Fitness Landscape Metrics
Algorithm recommendation using metalearning
Learning Method of the SIC Fuzzy Inference Model - Genki Ohashi - ICRC San Mateo, 2019
Is Your Algorithm Dangerous? Lyria Bennett Moses - Ignite: Sections Congress 2017
Learning through Deterministic Assignment of Hidden Parameter
Co-Design of Algorithms & Hardware for DNNs - Vivienne Sze - LPIRC 2019
Genetic Programming Hyper-heuristics for Combinatorial Optimisation: Yi Mei CIS Webinar
How Symmetry Constrains Evolutionary Optimizers: A Black Box Differential Evolution Case Study - IEEE Congress on Evolutionary Computation 2017
Combinatorial Sleeping Bandits with Fairness Constraints - Bo Ji - IEEE Sarnoff Symposium, 2019
Some Recent Work in Computational Intelligence for Software Engineering
Van Jacobson: The Slow-Start Algorithm
A Bayesian Approach for Spatial Clustering - IEEE CIS Webinar
Ponnuthurai Nagaratnam Suganthan - Differential Evolution
Multiobjective Quantum-inspired Evolutionary Algorithm and Preference-based Solution Selection Algorithm
IROS TV 2019- How to Build a Robot: Vision Based Estimation of Driving Energy for Planetary Rovers
Development of Quantum Annealing Technology at D-Wave Systems - 2018 IEEE Industry Summit on the Future of Computing
Quantum Annealing: Current Status and Future Directions - Applied Superconductivity Conference 2018
In this paper, we present a novel scheduling algorithm targeted toward minimizing the average execution time of control-flow intensive behavioral descriptions. Our algorithm uses a control/data flow graph model, which preserves the parallelism inherent in the application. It explores previously unexplored regions of the solution space by its ability to overlap the schedules of independent iterative constructs, whose bodies share resources. It also incorporates well known optimization techniques like loop unrolling in a natural fashion. This is made possible by a general loop-handling technique, which we have devised. Application of the algorithm to several common benchmarks demonstrates up to 4.8-fold improvement in expected schedule length over existing scheduling algorithms, without paying a price in terms of the best and worst case schedule lengths required to execute the behavioral description (in fact, frequently, the best/worst case schedule lengths are also better for our algorithm).
In this paper, a high efficient dynamic scheduling algorithm is developed to schedule a set of multi-thread on realtime multiprocessor systems. The algorithm divides two grades schedule. The one-grade-schedule inserts the new thread into thread-queue of thread-queue matrix according to the restriction rules and insertion rules, the two-grade-schedule places some threads chose from thread matrix into two-grade-windows, and then assigns multiple threads of two-grade-windows to processors concurrently reasonably. It has proved that this algorithm has higher efficiency and good effect in same structure multiprocessing system for multi-thread concurrent scheduling.
For scheduling messages in networked control system (NCS), the characters of messages in NCS are analyzed firstly in this paper. The message models are given and the relationship of messages is studied. Non pre-emptive EDF (earliest deadline first) is selected for scheduling messages and the method for realizing the scheduling algorithm is presented based on token control. The schedulability of messages is investigated and schedulable condition is given. According to the relationships of submessages, the submessage deadlines are optimized to increase the maximal utilization of network and the algorithm for computing optimal deadlines is prevented. The simulation results show that the algorithms prevented in this paper are effective.
With the advent of powerful network processors (NPs) in the market, many computation-intensive tasks such as routing table look-up, classification, IPSec, and multimedia transcoding can now be accomplished more easily in a router. An NP consists of a number of on-chip processors to carry out packet level parallel processing operations. Ensuring good load balancing among the processors increases throughput. However, such multiprocessing also gives rise to increased out-of-order departure of processed packets. In this paper, we first propose an Ordered Round Robin (ORR) scheme to schedule packets in a heterogeneous network processor assuming that the workload is perfectly divisible. The processed loads from the processors are ordered perfectly. We analyze the throughput and derive expressions for the batch size, scheduling time and maximum number of schedulable processors. To effectively schedule variable length packets in an NP, we propose a Packetized Ordered Round Robin (P-ORR) scheme by applying a combination of deficit round robin (DRR) and surplus round robin (SRR) schemes. We extend the algorithm to handle multiple flows based on a fair scheduling of flows depending on their reservations. Extensive sensitivity results are provided through analysis and simulation to show that the proposed algorithms satisfy both the load balancing and in-order requirements for parallel packet processing.
In the area of parallelizing compilers, considerable research has been carried out on data dependency analysis, parallelism extraction, as well as program and data partitioning. However, designing a practical, low complexity scheduling algorithm without sacrificing performance remains a challenging problem. A variety of heuristics have been proposed to generate efficient solutions but they take prohibitively long execution times for moderate size or large problems. In this paper, we propose an algorithm called FASTEST (Fast Assignment and Scheduling of Tasks using an Efficient Search Technique) that has O(e) time complexity, where e is the number of edges in the task graph. The algorithm first generates an initial solution in a short time and then refines it by using a simple but robust random neighborhood search. We have also parallelized the search to further lower the time complexity. We are using the algorithm in a prototype automatic parallelization and scheduling tool which compiles sequential code and generates parallel code optimized with judicious scheduling. The proposed algorithm is evaluated with several application programs and outperforms a number of previous algorithms by generating parallelized code with shorter execution times, while taking dramatically shorter scheduling times. The FASTEST algorithm generates optimal solutions for a majority of the test cases and close-to-optimal solutions for the rest.
In firm real time environments in which tasks must complete by their deadlines if they are to be of any value to the system, it is known that no uniprocessor online scheduling algorithm can guarantee to perform particularly well under conditions of overload as compared to clairvoyant algorithms. The article explores the issue of designing online scheduling algorithms that use multiple processors to compensate for their lack of clairvoyance. In particular, it is shown that given enough processors, online scheduling algorithms can be designed with performance guarantees arbitrarily close to that of optimal clairvoyant uniprocessor scheduling algorithms.
We develop a general model, called latency-rate servers (/spl Lscr//spl Rscr/ servers), for the analysis of traffic scheduling algorithms in broadband packet networks. The behavior of an /spl Lscr//spl Rscr/ server is determined by two parameters-the latency and the allocated rate. Several well-known scheduling algorithms, such as weighted fair queueing, virtualclock, self- clocked fair queueing, weighted round robin, and deficit round robin, belong to the class of /spl Lscr//spl Rscr/ servers. We derive tight upper bounds on the end-to-end delay, internal burstiness, and buffer requirements of individual sessions in an arbitrary network of /spl Lscr//spl Rscr/ servers in terms of the latencies of the individual schedulers in the network, when the session traffic is shaped by a token bucket. The theory of /spl Lscr//spl Rscr/ servers enables computation of tight upper bounds on end-to-end delay and buffer requirements in a heterogeneous network, where individual servers may support different scheduling architectures and under different traffic models.
We consider a graph theoretical model and study a parallel implementation of the well-known Gaussian elimination method on parallel distributed memory architectures, where the communication delay for the transmission of an elementary data is higher than the computation time of an elementary instruction. We propose and analyze two low-complexity algorithms for scheduling the tasks of the parallel Gaussian elimination on an unbounded number of completely connected processors. We compare these two algorithms with a higher-complexity general-purpose scheduling algorithm, the DSC heuristic, proposed by A. Gerasoulis and T. Yang (1993).
A new economic order quantity model is developed for multi-item and multi- storehouse with limited funds, limited storage capacity and stochastic demand. The model is proved to be a nonlinear convex programming. For finding the optimal replenishment schedule, we design a modified algorithm that combines Rosen's gradient projection method and Armijo-Goldstein line search method. A numerical example is presented to illustrate the solution procedure
The authors describe a novel algorithm that combines the hardware scheduling and component selection phases for high level synthesis. The algorithm improves on previous work in scheduling, by being able to simultaneously select components from a given library. This enlarges the design space, resulting in better optimized designs. Experimental results on the elliptic filter benchmark demonstrate that exploiting all available components in the library results in designs with smaller area compared to designs produced by scheduling with a single implementation for each component type.<<ETX>>
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