Conferences related to SRAM chips

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

The ICASSP meeting is the world's largest and most comprehensive technical conference focused on signal processing and its applications. The conference will feature world-class speakers, tutorials, exhibits, and over 50 lecture and poster sessions.


2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

The IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in the area of asynchronous design.


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Periodicals related to SRAM chips

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


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Most published Xplore authors for SRAM chips

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Xplore Articles related to SRAM chips

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Dual Port Sram - Data In Buffer

Dual Port Sram - Data In Buffer, 12/15/2011

Course content reaffirmed: 06/2015--There are several important timings that must be considered when designing the Data In Buffer that go beyond amplifying the input signal to drive the data to be written into the bit cell. The control timing must be such that the hold time for data in from the customer can be zero and not cause a change ...


Dual Port SRAM- Sensing Scheme

Dual Port SRAM- Sensing Scheme, 09/15/2011

Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that ...


Dual Port SRAM - Writing Bit Cell During Word Line Collision

Dual Port SRAM - Writing Bit Cell During Word Line Collision, 10/15/2011

Course content reaffirmed: 06/2015--The interaction in the array between the two ports can have some adverse effects that must be evaluated when designing a Dual Port SRAM, especially when one of the ports is doing a write. This tutorial takes a close look at a Word Line collision" that occurs when one port is writing while the other port is ...


Dual Port SRAM Bit Line Coupling Between Ports

Dual Port SRAM Bit Line Coupling Between Ports, 01/15/2012

Course content reaffirmed: 06/2015--The influence that one port can have on the other port bit line can be a subtle, yet costly problem if not fully evaluated, and can in fact result in the design not working. Capacitive coupling between neighboring bit lines must be properly modeled and evaluated to determine their impact based on the different conditions that can ...


Dual Port SRAM - Row Decoder

Dual Port SRAM - Row Decoder, 01/15/2014

Course content reaffirmed: 06/2015--Since there are 2 ports in this design, there must be 2 Row Decoders - one for each port. A big portion of the challenge is to be able to lay out the both Row Decoders and have each one be able to interface with every row of bit cells. I addition to that, the inputs to ...


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Educational Resources on SRAM chips

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IEEE-USA E-Books

  • Dual Port Sram - Data In Buffer

    Course content reaffirmed: 06/2015--There are several important timings that must be considered when designing the Data In Buffer that go beyond amplifying the input signal to drive the data to be written into the bit cell. The control timing must be such that the hold time for data in from the customer can be zero and not cause a change on the pin to propagate all the way to the bit cell and disturb what was just written. This tutorial makes a deeper evaluation of the timing paths that must be considered between clock and data in.

  • Dual Port SRAM- Sensing Scheme

    Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that can generate a logic output that is rail to rail. The read path from the bit line through the read select circuitry to the amplification of the signal at the sense amp output is presented in this tutorial.

  • Dual Port SRAM - Writing Bit Cell During Word Line Collision

    Course content reaffirmed: 06/2015--The interaction in the array between the two ports can have some adverse effects that must be evaluated when designing a Dual Port SRAM, especially when one of the ports is doing a write. This tutorial takes a close look at a Word Line collision" that occurs when one port is writing while the other port is reading the same row. SPICE simulation waveforms will be evaluated showing the interaction that can occur through the bit cell and affect what happens on the bit lines between the two ports. The situation where both ports access the same bit cell while one port is reading and the other port is writing is also evaluated."

  • Dual Port SRAM Bit Line Coupling Between Ports

    Course content reaffirmed: 06/2015--The influence that one port can have on the other port bit line can be a subtle, yet costly problem if not fully evaluated, and can in fact result in the design not working. Capacitive coupling between neighboring bit lines must be properly modeled and evaluated to determine their impact based on the different conditions that can occur in a dual port. This tutorial evaluates the worst case circumstances that can cause the differential during a read to be degraded - such as writing from one port while reading from the other, data dependency and bit cell location.

  • Dual Port SRAM - Row Decoder

    Course content reaffirmed: 06/2015--Since there are 2 ports in this design, there must be 2 Row Decoders - one for each port. A big portion of the challenge is to be able to lay out the both Row Decoders and have each one be able to interface with every row of bit cells. I addition to that, the inputs to from the address buffers associated with each port must be considered in how they are placed in the layout.

  • Dual Port Sram - Write Path

    Course content reaffirmed: 06/2015--The circuits in the write path from the bit cell through the write drivers and down to the write select circuitry are discussed. Specific analysis is done with one port writing while the other port is reading from the same row. The decoding approach for determining which bit line is driven low for a write is compared to the decoding required for reading the selected bit line and passing it out to the data out pin. Timing relationships between the key signals for doing a write will be evaluated from SPICE simulations.

  • Dual Port SRAM - Data Out Buffer

    Course content reaffirmed: 06/2015--There are several important features required for how the data output is controlled and how it drives the data out pin that the customer connects to. This Dual Port tutorial describes the design of the Data Output Buffer and how it is used to latch the data out and hold it valid even into the next cycle. Special pre-charge functions are designed into the buffer to allow for easy ripple thru of data to the output once the sense amp asserts but still will latch and hold the data after it goes back into pre-charge. The design of other features such as the use of OEZ to control when the output is in high Z is discussed. Schematics and waveforms from SPICE simulations will be presented, and the complete read path from when the word line asserts to the output of data at the pin will be evaluated.

  • SRAM Core Modeling Methodology for Efficient Power Delivery Analysis

    It is common that high performance integrated circuit today achieves faster processing speed by padding as many memory cells or SRAM (static random access memory) in its core logic as possible. The build-in SRAM cell allows the PCH (platform controller hub) to access the nearest data storage with least latency. While the SRAM cells are aggressively populating the PCH core, the total chip power consumption is increasing. Power gating technology becomes a juicy implementation on these SRAM to turn off the power when it is not in used. In this project, the computing power savings have achieved ~900mW and proven to be a good strategy for preserving mobile computing power and extension of battery life span. However, the aggressive implementation of power gating and un-gating technology, if not understood fully, will be leading to uncontrollable transient ac noise on the power delivery network (PDN) and ultimately impacting the PCH core performance. This paper describes a comprehensive approach in characterizing and optimizing the PDN invoked by the multiple SRAM cells power gate/un-gate dynamically. By deriving the worst case possible configurations on which each power gate/un-gate could happen within the same power supply domain, it allows the designer to first guesstimate how severe each transient droop will occur. This is followed by customizing the SRAM cells using a configurable clock latency to offset the power un-gate timing and spreading out the SSO (simultaneous switching output) noise such that the voltage droop is contained within an allowable budget. Secondary effect such as the sudden lost of capacitance reservoir following the power gate of SRAM and the appropriate approach in quantifying the SRAM capacitance during power gated and un-gated is discussed in this paper too. The paper is concluded with post-silicon measurement of SRAM power gate/un- gate transient characterization behavior, showing a good correlation to within 96% match to the pre-silicon estimate. It is a proven method and can be leveraged to many processor and chipset designs which are looking for aggressive power savings while preserving the core performance to its optimum.

  • A concurrent operating CDRAM for low cost multi-media

    This paper describes a concurrent operating cache DRAM (CDRAM) for low cost multi-media systems, in which the program and graphic data coexist in the main memory. The concurrent operation of the DRAM and SRAM completely removes the idle cycles. As a result, the average access time is equal to the SRAM access time of 6.5 ns with 0.6 /spl mu/m CMOS process. The flash write and direct read/write are also useful for the multi-media systems.

  • Static random access memory using high electron mobility transistors

    A 4-bit fully decoded static random access memory (RAM) has been designed and fabricated using high electron mobility transistors (HEMT's) with a direct- coupled FET logic approach. The circuit incorporates approximately 50 logic gates. A fully operating memory circuit was demonstrated with an access time of 1.1 ns and a minimum WRITE-enable pulse of less than 2-ns duration at room temperature. This memory consumes a total power of 14.89 mW and 87.8 µW per memory cell.



Standards related to SRAM chips

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No standards are currently tagged "SRAM chips"


Jobs related to SRAM chips

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