Conferences related to SONOS devices

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2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE 11th International Memory Workshop (IMW)

The IMW is a unique forum for specialists in all aspects of memory (nonvolatile & volatile)microelectronics and people with different backgrounds who wish to gain a better understandingof the field. The morning and afternoon technical sessions are organized in a manner thatprovides ample time for informal exchanges amongst presenters and attendees. The eveningpanel discussions will address hot topics in the memory and memory system field. Papers aresolicited in all aspects of semiconductor memory technology (Flash, DRAM, SRAM, PCRAM,RRAM, MRAM, embedded memory, and other NV memories).


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAM


2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC)

Covers all electronic materials and devices fields that involve nanotechnology

  • 2017 IEEE 12th Nanotechnology Materials and Devices Conference (NMDC)

    This conference serves as a perfect platform on which scientists and engineers can present and highlight some of the key advances in the research topics relevant to nanoscience and nanotechnology.

  • 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC)

    IEEE NMDC 2016 aims to foster communication between physicists, chemists, microbiologists and engineers from academics and industry, interested in nanodevices and nanostructured materials, advanced preparation techniques, new material properties, standards and safety issues of nanotechnology, in computer simulations and theoretical work. Interdisciplinary exchange between scientists and contributions from industrial researchers will stimulate gather knowledge and help inspire a new perspective in industrial applications on this exciting area.

  • 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC)

    IEEE-NMDC 2015 is the 10th Nanotechnology Materials and Devices Conference. Published papers in the conference will be indexed at IEEExplore. A contest for the best paper award will be held and awards will be given at the end of the conference. Authors of the best papers of each track will be invited to submit their extended article version to: IEEE Transactions on Nanobioscience, IEEE Nanotechnology Magazine, and IEEE Transaction on Nanotechnology.

  • 2014 IEEE 9th Nanotechnology Materials and Devices Conference (NMDC)

    IEEE-NMDC 2014 wants to be a forum of discussion about nanotechnology, with a special focus on materials and devices. Topics:-Graphene and carbon nanotubes based materials and devices-Materials and devices for nanoelectronics-Materials and devices for energy and environmental applications-Nanostructures for future generation solar cells-Ion beam synthesis and modification of nanostructures-Advanced characterization of nanomaterials and nanostructures-Modeling and simulation of nanomaterials, structures, and devices-Metamaterials and plasmonic devices-Photonic materials and devices-Organic semiconductor materials, devices and applications-Nanostructures of oxide semiconductor materials-III-V semiconductors nanomaterials-Nanostructures for water purification-Nanomaterials and devices for biomedical applications-Standards and safety issues of nanotechnology-Fundamentals and applications of nanotubes, nanowires, quantum dots and other low dimensional materials

  • 2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)

  • 2012 IEEE 7th Nanotechnology Materials and Devices Conference (NMDC)

    Graphene and Nanotube Based Materials and Devices; MEMS/NEMS for Bio-Nanotechnology; Characterization and Simulation of Nanomaterials and Nanostructures; Materials and Devices for Nanoelectronics, Nano-Optics; Materials and Devices for Energy and Environmental Applications.

  • 2011 IEEE Nanotechnology Materials and Devices Conference (NMDC)

    NMDC aims to develop critical assessment of existing work and future directions in nanotechnology research including nanomaterials and fabrications, nanoelectronics, nanophotonics, devices, and integration. This conference will bring together key researchers from every sector in the nanotechnology research field, with a special focus on materials and devices.

  • 2010 IEEE Nanotechnology Materials and Devices Conference (NMDC)

    NMDC aims to develop critical assessment of existing work and future directions in nanotechnology research including nanomaterials and fabrications, nanoelectronics, nanophotonics, devices, and integration. This conference will bring together key researchers from all over the world and from every sector of academy and industry in the nanotechnology research field, with a special focus on materials and devices.

  • 2009 IEEE Nanotechnology Materials and Devices Conference (NMDC)

    NMDC aims to develop critical assessment of existing work and future directions in nanotechnology research including nanomaterials and fabrications, nanoelectronics, nanophotonics, devices, and integration. This conference will bring together key researchers from all over the world and from every sector of academy and industry in the nanotechnology research field, with a special focus on materials and devices.

  • 2008 2nd Nanotechnology Materials and Devices Conference (NMDC)

    NMDC aims to develop critical assessment of existing work and future directions in nanotechnology research including nanomaterials and fabrications, nanoelectronics, nanophotonics, devices, and integration. This conference will bring together key researchers from all over the world and from every sector of academy and industry in the nanotechnology research field, with a special focus on materials and devices.

  • 2006 Nanotechnology Materials and Devices Conference (NMDC)


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Periodicals related to SONOS devices

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Information Theory, IEEE Transactions on

The fundamental nature of the communication process; storage, transmission and utilization of information; coding and decoding of digital and analog communication transmissions; study of random interference and information-bearing signals; and the development of information-theoretic techniques in diverse areas, including data communication and recording systems, communication networks, cryptography, detection systems, pattern recognition, learning, and automata.


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


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Most published Xplore authors for SONOS devices

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Xplore Articles related to SONOS devices

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A New Buried Channel EEPROM Device

50th Annual Device Research Conference, 1992

None


Session 11

2009 International Symposium on VLSI Technology, Systems, and Applications, 2009

Start of the above-titled section of the conference proceedings record.


Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler–Nordheim Tunneling Program/Erase Operation

IEEE Electron Device Letters, 2009

Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P- and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but ...


Study of Warm-Electron Injection in Double-Gate SONOS by Full-Band Monte Carlo Simulation

IEEE Electron Device Letters, 2008

In this letter, we investigate warm-electron injection in a double-gate SONOS memory by means of 2-D full-band Monte Carlo simulations of the Boltzmann transport equation. Electrons are accelerated in the channel by a drain-to- source voltage <i>V</i> <sub>DS</sub> smaller than 3 V, so that programming occurs via electrons tunneling through a potential barrier whose height has been effectively reduced by ...


A Highly Reliable Multi-level and 2-bit/cell Operation of Wrapped-Select-Gate (WSG) SONOS Memory with Optimized ONO Thickness

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2007

High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride- silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily ...


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Educational Resources on SONOS devices

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IEEE-USA E-Books

  • A New Buried Channel EEPROM Device

    None

  • Session 11

    Start of the above-titled section of the conference proceedings record.

  • Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler–Nordheim Tunneling Program/Erase Operation

    Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P- and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but at the cost of higher P-state retention loss. The choice of SiN stoichiometry to optimize CTF memory performance and reliability is discussed.

  • Study of Warm-Electron Injection in Double-Gate SONOS by Full-Band Monte Carlo Simulation

    In this letter, we investigate warm-electron injection in a double-gate SONOS memory by means of 2-D full-band Monte Carlo simulations of the Boltzmann transport equation. Electrons are accelerated in the channel by a drain-to- source voltage <i>V</i> <sub>DS</sub> smaller than 3 V, so that programming occurs via electrons tunneling through a potential barrier whose height has been effectively reduced by the accumulated kinetic energy. Particle energy distribution at the semiconductor/oxide interface is studied for different bias conditions and different positions along the channel. The gate current is calculated with a continuum-based postprocessing method as a function of the particle distribution obtained from Monte Carlo simulation. Simulation results show that the gate current increases by several orders of magnitude with increasing drain bias, and warm-electron injection can be an interesting option for programming when short-channel effects prohibit the application of larger drain bias.

  • A Highly Reliable Multi-level and 2-bit/cell Operation of Wrapped-Select-Gate (WSG) SONOS Memory with Optimized ONO Thickness

    High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride- silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well V<sub>th</sub> distribution is also presented. High program/erase speed (10 us/5 ms) and low programming current (3.5 u/A) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.

  • A$\hbox{TiSi}_{2}/\hbox{Si}$Heteronanocrystal Memory Operated With Hot Carrier Injections

    The programming and erasing of a TiSi2/Si heteronanocrystal memory were carried out by channel hot electron injection and drain side hot hole injection, respectively. Compared to an Si nanocrystal memory, a TiSi2/Si heteronanocrystal memory exhibits much better writing/erasing efficiency and higher writing/erasing saturation level. The retention transient process indicates that the TiSi2/Si heteronanocrystal memory has a very slow charge loss mechanism. The result of the localization of charge shows that a reverse read leads to a higher threshold voltage shift, which is almost not dependent on the amplitude of the read voltages.

  • Single-chip Integration of SRAM and Non-volatile Memory using Bit-line Sharing

    A new memory architecture integrating SRAM and Flash within the same array is presented and demonstrated in a standard 0.25mum CMOS process with a memory access time of 20ns. Differential pair Flash cells with low programming current share the same bit-lines as SRAM cells within the same array. This enables row-to-row transfer of data between Flash and SRAM cells as well as access data through I/O directly, in return improving speed and lowering power. Area is saved through the shared usage of column decoding, sense- amplifier, and write-driver circuitry

  • A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals

    In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot- electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10<sup>-7</sup> A by the band-to-band tunneling current. A much larger memory window (&gt; 12 V) and good data retention time (&gt; 10<sup>8</sup> s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.

  • A scalable, low voltage, low cost SONOS memory technology for embedded NVM applications

    A novel low cost, eNVM technology is presented which has the lowest program/erase voltage reported to date. It is based on the integration of a SONOS based NVM module into a foundry CMOS process with only 3 additional masks and no additional HV oxide. An optimized integration scheme ensures that the CMOS device parameters of the eNVM process are closely matched to baseline process. Even with the low 7.5V program/erase voltage, excellent reliability has been demonstrated meeting automotive data retention requirements and 100k cycle endurance on a 4.5Mbit flash memory macro.

  • A 90nm Embedded 2-Bit Per Cell Nanocrystal Flash EEPROM

    A two bit/cell embedded nanocrystal bitcell with low write current SSI program and tunnel erase in which nanocrystals are located under dedicated control gates has been demonstrated. Write bias conditions which mitigate gate disturb in a top erase capable bitcell have been confirmed



Standards related to SONOS devices

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No standards are currently tagged "SONOS devices"


Jobs related to SONOS devices

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