Quantum capacitance

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Quantum capacitance (density) is a physical value first introduced by Serge Luryi (1988) to describe the 2D-electronic systems in silicon surfaces and AsGa junctions. (Wikipedia.org)






Conferences related to Quantum capacitance

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2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation


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Periodicals related to Quantum capacitance

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Electromagnetic Compatibility, IEEE Transactions on

EMC standards; measurement technology; undesired sources; cable/grounding; filters/shielding; equipment EMC; systems EMC; antennas and propagation; spectrum utilization; electromagnetic pulses; lightning; radiation hazards; and Walsh functions


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


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Most published Xplore authors for Quantum capacitance

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Xplore Articles related to Quantum capacitance

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Theoretical study of quantum squeezing to graphene based drum resonator

2015 International Conference on Manipulation, Manufacturing and Measurement on the Nanoscale (3M-NANO), 2015

Based on reported study of quantum squeezing on doubly clamped structure, we performed comprehensive investigation on graphene drum resonator. Two key criteria of achieving squeezing states, zero-point displacement uncertainty and squeezing factor of strained multilayer graphene drum resonator are studied. The research fills gap of quantum squeezing to drum resonator for implementing graphene-based nanoscale transducers with ultra-high sensitivity that can ...


First steps towards a quantum capacitance standard at METAS

Conference Digest Conference on Precision Electromagnetic Measurements, 2002

In the 5th framework program of the European Commission, several Metrology Institutes have teamed up in a project (COUNT) aimed at the realization of a primary standard of capacitance based on single electron resistive pumps. In this paper, we report the first steps towards the realization of such a quantum capacitance standard at METAS. The measurement setup is described and ...


Full quantum simulation, design, and analysis of Si tunnel diodes, MOS leakage and capacitance, HEMTs, and RTDs

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001

The Nanoelectronic Engineering Modeling software (NEMO) has been used to model the quantum electron and hole transport and charge in a wide variety of material systems and semiconductor devices. This paper provides an overview of NEMO's current status, its applications, and its theoretical extensions.


Modeling and performance analysis of ballistic carbon nanotube field effect transistor (CNTFET)

Recent Advances in Space Technology Services and Climate Change 2010 (RSTS & CC-2010), 2010

In this paper, we have proposed the compact modeling of ballistic CNTFET and the performance analysis of the developed model using various characteristics. The carbon nanotube transistors (CNTFET) are currently considered and most promising component to replace the generation of MOSFET transistor, especially in order to surpass the short channel effects in the component. For this new generation of transistor ...


A novel compact model of quantum effects in scaled SOI and double-gate MOSFETs

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125), 2000

Quantum-mechanical (QM) confinement of inversion-layer carriers significantly affects the threshold voltage and gate capacitance of highly scaled MOSFETs. In bulk-Si and partially depleted (PD) SOI (n)MOSFETs, the confinement is in the potential well defined by the gate-oxide barrier (which is virtually infinite) and the silicon conduction (or valence) band (the steep gradient of which defines the high transverse electric field, ...


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Educational Resources on Quantum capacitance

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IEEE.tv Videos

IMS 2015: Edward Tong - John Tucker Special Tribute - Ultra-wide IF Bandwidth - The Next Frontier for SIS Receivers
From the Quantum Moore's Law toward Silicon Based Universal Quantum Computing - IEEE Rebooting Computing 2017
Q&A with Travis Humble: IEEE Rebooting Computing Podcast, Episode 27
Quantum Technologies in Europe: The Quantum Flagship Initiative - Applied Superconductivity Conference 2018
Physical Restraints on Quantum Circuits - IEEE Rebooting Computing 2017
Quantum Accelerators for High-Performance Computing Systems - IEEE Rebooting Computing 2017
Superconducting Quantum Computing in China - Applied Superconductivity Conference 2018
Advanced Capacitive Sensing for Consumer, Industrial, and Automotive Applications - Lecture by Dr. Hans Klein
Challenges and Opportunities of the NISQ Processors (Noisy Intermediate Scale Quantum Computing) - 2018 IEEE Industry Summit on the Future of Computing
Developing Our Quantum Future - Krysta Svore Keynote - ICRC San Mateo, 2019
Steep Slope Devices: Advanced Nanodevices - Nicolo Oliva at INC 2019
An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo - IEEE Rebooting Computing 2017
Parallel Quantum Computing Emulation - Brian La Cour - ICRC 2018
Nanophotonic Devices for Quantum Information Processing: Optical Computing - Carsten Schuck at INC 2019
D-Wave Quantum Computer: Technology Update - Fabio Altomare - ICRC San Mateo, 2019
The Prospects for Scalable Quantum Computing with Superconducting Circuits - Applied Superconductivity Conference 2018
Part 2: Workshop on Benchmarking Quantum Computational Devices and Systems - ICRC 2018
IEEE Honorary Membership - Anton Zeilinger and Mike Lazaridis - 2018 IEEE Honors Ceremony
Electronic Systems for Quantum Computation - David DiVincenzo: 2016 International Conference on Rebooting Computing
Record-high Secret Key Rate for Joint Classical & Quantum Transmission Over 37-core Fiber - Beatrice Da Lio - Closing Ceremony, IPC 2018

IEEE-USA E-Books

  • Theoretical study of quantum squeezing to graphene based drum resonator

    Based on reported study of quantum squeezing on doubly clamped structure, we performed comprehensive investigation on graphene drum resonator. Two key criteria of achieving squeezing states, zero-point displacement uncertainty and squeezing factor of strained multilayer graphene drum resonator are studied. The research fills gap of quantum squeezing to drum resonator for implementing graphene-based nanoscale transducers with ultra-high sensitivity that can be potentially utilized to detect a variety of sensing targets, including atomic force, single biological molecule, and gravitational wave.

  • First steps towards a quantum capacitance standard at METAS

    In the 5th framework program of the European Commission, several Metrology Institutes have teamed up in a project (COUNT) aimed at the realization of a primary standard of capacitance based on single electron resistive pumps. In this paper, we report the first steps towards the realization of such a quantum capacitance standard at METAS. The measurement setup is described and the stability diagram of the electron pump, measured at an electronic temperature of 160 mK, is shown. These preliminary results are promising for the future of the experiment.

  • Full quantum simulation, design, and analysis of Si tunnel diodes, MOS leakage and capacitance, HEMTs, and RTDs

    The Nanoelectronic Engineering Modeling software (NEMO) has been used to model the quantum electron and hole transport and charge in a wide variety of material systems and semiconductor devices. This paper provides an overview of NEMO's current status, its applications, and its theoretical extensions.

  • Modeling and performance analysis of ballistic carbon nanotube field effect transistor (CNTFET)

    In this paper, we have proposed the compact modeling of ballistic CNTFET and the performance analysis of the developed model using various characteristics. The carbon nanotube transistors (CNTFET) are currently considered and most promising component to replace the generation of MOSFET transistor, especially in order to surpass the short channel effects in the component. For this new generation of transistor (CNTFET) with very short channel, the majority of models describing electrical conduction based on the process of ballistic transport. We propose design-oriented compact models for ballistic CNTFET. We are interested more particularly to the drain current and the quantum capacitance as a function of the gate voltage (VGS), for various values of the nanotube diameter and the oxide thickness. These models have been simulated and the results that are obtained were in excellent agreement with the theoretical calculations.

  • A novel compact model of quantum effects in scaled SOI and double-gate MOSFETs

    Quantum-mechanical (QM) confinement of inversion-layer carriers significantly affects the threshold voltage and gate capacitance of highly scaled MOSFETs. In bulk-Si and partially depleted (PD) SOI (n)MOSFETs, the confinement is in the potential well defined by the gate-oxide barrier (which is virtually infinite) and the silicon conduction (or valence) band (the steep gradient of which defines the high transverse electric field, which controls the effect) (Stern, 1972). In ultra-thin-film fully depleted (FD) SOI and double-gate (DG) MOSFETs, the well is defined by the front- and back-gate oxide barriers, but the quantum effect can be significantly influenced by the electric field in the Si film (Majkusiak et al, 1998). Furthermore, as the film thickness (t/sub Si/) is increased, this influence becomes predominant as in the bulk-Si and PD/SOI devices. In this paper, we present a comprehensive compact model for the quantum-confinement effects for arbitrary t/sub Si/. The model, verified by numerical simulation results obtained with a self-consistent Schrodinger- Poisson solver (SCHRED; Vasileska et al, 2000), leads to characterizations of the threshold-voltage increase due to the carrier-energy quantization and the gate-capacitance reduction due to the perturbed carrier distribution.

  • 2D tunnel transistors for ultra-low power applications: Promises and challenges

    Summary form only given. Tunnel field-effect (TFET) transistors [1] are among the most promising devices for future low-power electronics [2]. However, TFETs usually suffer from low ON-current values. Recently, it has been shown that TFETs made from 2D materials, can in principle, provide high ON-currents due to their tight gate control [3]. A better gate control over the channel increases the electric field at the tunnel junction, which results in a higher performance [3, 8]. 2D TFETs are known as steep subthreshold swing (SS) devices with the goal of lowering V<sub>DD</sub>. However, in the previous atomistic simulations of transition metal dichalcogenide (TMD) TFETs a V<sub>DD</sub> of 0.5V has been used [3] which is still a high value for ultra-low power applications. In this work, the performance of ultra-low power WTe<sub>2</sub> TFETs with a V<sub>DD</sub> of 0.25V is studied. Comparing the performances of WTe<sub>2</sub> TFETs with V<sub>DD</sub> of 0.25V and 0.5V exhibits the promises and the challenges ahead of lowering V<sub>DD</sub> in the ultra-low power TFETs.

  • Microprobe Integrated with Single-Electron Transistor for Magnetic Resonance Force Microscopy

    In this paper, a novel probe with an integrated radio frequency single- electron transistor (rf-SET) for magnetic resonance force microscopy operated at low temperatures is proposed and fabricated. By using the charge sensitivity of the rf-SET, the displacement of a cantilever can be detected from the capacitance variation between the quantum island and the gate formed on the cantilever with high sensitivity. The rf-SET using a Cr thin film isolated with tunneling junction of a thin silicon dioxide film was fabricated on the basis of electron beam lithography and self-aligned island formation.

  • Analysis of graphene field effect transistor based current mirrors

    Current mirrors are important basic building blocks of analog electronic circuits. In this paper graphene field effect transistor (GFET) based basic and cascode current mirrors are studied. Drain current equations of the GFET model are coded with Verilog-A language and integrated to SPICE simulator. DC output characteristics of current mirror circuits are analyzed and compared for both configuration with the help of simulation results. AC analysis is also performed and frequency response of the circuits are observed. The simulation results show that GFET based current mirrors can operate properly, however there are some drawbacks to overcome.

  • Extraction of the Interface State Density of Top-Gate Graphene Field-Effect Transistors

    Novel electrical measurement method, discharge current analysis (DCA), is introduced to extract the density and energy distribution of charge traps at the dielectric interface of top-gate graphene field-effect transistors. Using DCA method, the highest charge trap density ~1013(cm-2· eV-1) is extracted at Fermi level ~0.4 eV. This is the first quantitative estimation of trap density at a specific Fermi level of graphene.

  • A highly stable tunable cryogenic capacitor

    In order to realize a quantum capacitance standard, a highly stable vacuum-gap cryogenic capacitor based on a coaxial design has been developed. A tuning mechanism allows to adjust the room temperature value of the capacitance to obtain a value of 1 pF at 4.2 K. At low temperature, the difference between the measured and the target value is smaller than 30 ppm. This summary describes the main characteristics of this tunable capacitor.



Standards related to Quantum capacitance

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IEEE Application Guide for Capacitance Current Switching for AC High-Voltage Circuit Breakers

This project will revise the application guide for capacitance current switching for high-voltage circuit breakers rated in accordance with IEEE C37.04 and listed in C37.06. It is intended to supplement C37.010.


IEEE Standard for Backplane Electrical Performance


IEEE Standard Test Procedures for Semiconductor X-Ray Energy Spectrometers


Standard for AC High-Voltage Circuit Breakers Rated on a Symmetrical Current Basis - Preferred Ratings and Related Required Capabilities for Voltages above 1000 Volts

This standard applies to all indoor and outdoor types of AC high-voltage circuit breakers rated above 1000 volts and rated on a symmetrical current basis.


Standard Requirements, Terminology, and Test Code for Bushings for DC Applications Rated 110 kV BIL and Above

This standard applies to outdoor and indoor power apparatus dc bushings of condenser type that have basic impulse insulation levels of 110 kV and above for use as components of oil-filled converter transformers and smoothing reactors, as well as air-to-air dc bushings. This standard does not apply to the following: a) High-voltage cable terminations (potheads) b) Bushings for instrument transformers ...



Jobs related to Quantum capacitance

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