Conferences related to Optimizing compilers

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE 29th International Symposium on Industrial Electronics (ISIE)

ISIE focuses on advancements in knowledge, new methods, and technologies relevant to industrial electronics, along with their applications and future developments.


2020 IEEE/ACM 42nd International Conference on Software Engineering (ICSE)

ICSE is the premier forum for researchers to present and discuss the most recent innovations,trends, outcomes, experiences, and challenges in the field of software engineering. The scopeis broad and includes all original and unpublished results of empirical, conceptual, experimental,and theoretical software engineering research.


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.


2019 34th IEEE/ACM International Conference on Automated Software Engineering (ASE)

The IEEE/ACM Automated Software Engineering (ASE) Conference series is the premier research forum for automated software engineering. Each year, it brings together researchers and practitioners from academia and industry to discuss foundations, techniques and tools for automating the analysis, design, implementation, testing, and maintenance of large software systems.



Periodicals related to Optimizing compilers

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Antennas and Wireless Propagation Letters, IEEE

IEEE Antennas and Wireless Propagation Letters (AWP Letters) will be devoted to the rapid electronic publication of short manuscripts in the technical areas of Antennas and Wireless Propagation.


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.



Most published Xplore authors for Optimizing compilers

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Xplore Articles related to Optimizing compilers

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Complex versus reduced instruction set computers

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1983

Recently, considerable controversy has arisen on the use of Reduced Instruction Set Computers (RISCs), when performing general purpose computing tasks. Beyond being the subject of an architecture debate, the concept of reduced instruction sets may have dramatic implications for VLSI design tradeoffs: design time, design methodology, performance and testing . . Panelists will discuss the merits of RISCs versus the ...


Precision architecture

Computer, 1989

The processor component of the Hewlett-Packard Precision Architecture system is described. The architecture's goals, how the architecture addresses the spectrum of general-purpose user information processing needs, and some architectural design tradeoffs are examined. Extendibility and longevity features are considered.<<ETX>>


Semantic Structures for Efficient Code Generation on a Stack Machine

Computer, 1977

Since the expression is the fundamental building block of any programming language, its evaluation is an integral part of program compilation and execution. In particular, the evaluation techniques and data structures are determined by the class of expressions acceptable by the language. This paper serves as a framework for expression evaluation on a stack machine by presenting a set of ...


A C compiler based methodology for implementing audio DSP applications on a class of embedded systems

2008 IEEE International Symposium on Consumer Electronics, 2008

This paper describes a methodology for a common task of audio application implementation from the referent C code to executable image targeting an audio fixed-point mid-scale DSPs. This methodology tries to efficiently cover the gap between the referent code and the assembler code by usage of the C compiler, which supports fixed-point types defined in C language extensions for the ...


Branch Merging For Effective Exploitation Of Instruction-level Parallelism

[1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25, 1992

None



Educational Resources on Optimizing compilers

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IEEE-USA E-Books

  • Complex versus reduced instruction set computers

    Recently, considerable controversy has arisen on the use of Reduced Instruction Set Computers (RISCs), when performing general purpose computing tasks. Beyond being the subject of an architecture debate, the concept of reduced instruction sets may have dramatic implications for VLSI design tradeoffs: design time, design methodology, performance and testing . . Panelists will discuss the merits of RISCs versus the more traditional instruction sets.

  • Precision architecture

    The processor component of the Hewlett-Packard Precision Architecture system is described. The architecture's goals, how the architecture addresses the spectrum of general-purpose user information processing needs, and some architectural design tradeoffs are examined. Extendibility and longevity features are considered.<<ETX>>

  • Semantic Structures for Efficient Code Generation on a Stack Machine

    Since the expression is the fundamental building block of any programming language, its evaluation is an integral part of program compilation and execution. In particular, the evaluation techniques and data structures are determined by the class of expressions acceptable by the language. This paper serves as a framework for expression evaluation on a stack machine by presenting a set of optimized algorithms and internal data structures developed during the implementation of several compilers for the Hewlett- Packard computer systems.

  • A C compiler based methodology for implementing audio DSP applications on a class of embedded systems

    This paper describes a methodology for a common task of audio application implementation from the referent C code to executable image targeting an audio fixed-point mid-scale DSPs. This methodology tries to efficiently cover the gap between the referent code and the assembler code by usage of the C compiler, which supports fixed-point types defined in C language extensions for the embedded processors. By relaying on C++ classes this methodology deliveries a possibility to debug a DSP compiler ready C code in a C++ environment (e.g. Visual C++). The methodology was successfully applied to several audio applications, such as Dolby Volume, SRS TSHD, SRS VIQ, and Audyssey Dynamic EQ, and their implementation to Cirrus Logic Coyote DSP family. Experience with those applications shows that this methodology greatly shortens time to market for DSP firmware product.

  • Branch Merging For Effective Exploitation Of Instruction-level Parallelism

    None

  • A Static Analysis of the NAG Library

    This paper reports results obtained from a static analysis of the NAG Mark 4 Fortran numerical algorithms library.

  • Transformation-based assessment for C programs

    In this paper, a new framework, AnalyseC, is proposed for assessing student programming exercises with an aim to free teachers from heavy assessment work and facilitate studentspsila learning. Based on code optimization techniques of compiler, such as inline expansion, data flow analysis and control flow analysis, AnalyseC has been designed to automatically assess programming assignments written in C language at semantic level. The prototype has been implemented in Java. To use the system, teachers are required to provide a simple model program for any given assessment item. The prototype of AnalyseC has been tested on a number of student programming exercises and assignments providing encouraging results.

  • ReCode: the design and re-design of the instruction codes for embedded instruction-set processors

    This abstract presents a design aid called ReCode, and describes its use in the analysis of existing instruction-set processors. ReCode allows the exploration of the relationship between the instruction-set and the corresponding application code of embedded processors. After analyzing the instruction-set and code, the designer can then use the set of editing functions to adjust the instruction set to the application code. ReCode is a window-based tool which has two modes of analysis: static and dynamic. In the static mode, the tool allows the user to analyze the correspondence between the use of assembly codes and the compiled application code. This allows the designer to identify codes which have poor utilization and make changes accordingly. As the tool works with an instruction-set specification which can be regenerated, the compiler is consequently retargeted automatically for any changes.

  • A fast algorithm for scheduling time-constrained instructions on processors with ILP

    Instruction scheduling is central to achieving performance in modern processors with instruction level parallelism (ILP). Classical work in this area has spanned the theoretical foundations of algorithms for instruction scheduling with provable optimality, as well as heuristic approaches with experimentally validated performance improvements. Typically, the theoretical foundations are developed in the context of basic-blocks of code. In this paper, we provide the theoretical foundations for scheduling basic-blocks of instructions with time-constraints, which can play an important role in compile-time ILP optimizations in embedded applications. We present an algorithm for scheduling unit-execution-time instructions on machines with multiple pipelines, in the presence of precedence constraints, release-times, deadlines, and latencies l/sub ij/ between any pairs of instructions i and j. Our algorithm runs in time O(n/sup 3//spl alpha/(n)), where /spl alpha/(n) is the functional inverse of the Ackermann function. It can be used construct feasible schedules for two classes of instances: (1) one pipeline and the latencies between instructions are restricted to the values of 0 and 1, and (2) arbitrary number of pipelines and monotone-interval order precedences. Our result can be seen as a natural extension of previous work on instruction scheduling for pipelined machines in the presence of deadlines.

  • An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler

    Power efficient SoC design for embedded applications requires several independent power-domains where the power of unused blocks can be turned off. An SoC for mobile phones defines 23 hierarchical power domains but most of the power domains are assigned for peripheral IPs that mainly use low-leakage high-V<sub>t</sub> transistors. Since high-performance multiprocessor SoCs use leaky low-V<sub>t</sub> transistors for CPU sections, leakage power savings of these CPU sections is a primary objective. We develop an SoC with 8 processor cores and 8 user RAMs (1 per core) targeted for power-efficient high- performance embedded applications. We assign these 16 blocks to separate power domains so that they can be independently be powered off. A resume mode is also introduced where the power of the CPU is off and the user RAM is on for fast resume operation. An automatic parallelizing compiler schedules tasks for each CPU core and also performs power management for each CPU core. With the help of this compiler, each processor core can operate at a different frequency or even dynamically stop the clock to maintain processing performance while reducing average operating power consumption. The compiler also executes power-off control of unnecessary CPU cores.



Standards related to Optimizing compilers

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No standards are currently tagged "Optimizing compilers"