Neuromorphic engineering

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Neuromorphic engineering or neuromorphic computing is a concept developed by Carver Mead, in the late 1980s, describing the use of very-large-scale integration (VLSI) systems containing electronic analog circuits to mimic neuro-biological architectures present in the nervous system. (Wikipedia.org)






Conferences related to Neuromorphic engineering

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2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

The ICASSP meeting is the world's largest and most comprehensive technical conference focused on signal processing and its applications. The conference will feature world-class speakers, tutorials, exhibits, and over 50 lecture and poster sessions.


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Periodicals related to Neuromorphic engineering

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Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems Magazine, IEEE


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Most published Xplore authors for Neuromorphic engineering

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Xplore Articles related to Neuromorphic engineering

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III Technological and Scientific Impact

The Deep Learning Revolution, None

None


Neuromorphic VLSI systems for visual information processing: drawbacks

1999 Third International Conference on Knowledge-Based Intelligent Information Engineering Systems. Proceedings (Cat. No.99TH8410), 1999

In this paper, the neuromorphic VLSI approach for visual processing and detection is presented. A brief history of neuromorphic vision systems is presented. The advantages and disadvantages of neuromorphic systems are highlighted and some of the major barriers towards realizing these systems are discussed. In particular, the implementation of early visual processing models using analogue VLSI is described and some ...


Adaptation in a VLSI model of a neuron

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999

We have designed, fabricated, and tested an analog very large-scale integrated (VLSI) circuit model of a biological neuron that implements self-adaptation of its parameters. We show that the addition of this self-adaptation to our model neuron can facilitate: (1) single parameter control over a multiparameter system; (2) stability of the system to fluctuations in parameters; and (3) coordinated modulation of ...


Designing spiking neural networks

2016 13th International Conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science (TCSET), 2016

The problem of design is the most important part of complex systems building. This is also true for spiking neural networks. In this paper, the next steps of SNN design are described: coding, selecting neuron model and learning algorithm, creating network architecture. Software and hardware solutions for simulating these networks are also discussed. We propose a range of evolution directions, ...


A new computing rule for neuromorphic engineering

2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 2015

Neuromorphic engineering has helped to build a brain-inspired intelligent paradigm based on VLSI, and to promise a new application space on smart devices. Throughout most of the state-of-the-art neuromorphic systems, including analog, digital, the mixed one, as well as some other memristor- based systems, the dominated computing rule in neuron is simply based on the linear-superposition operation of the excitatory ...


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Educational Resources on Neuromorphic engineering

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IEEE.tv Videos

Neuromorphic Chips - Kwabena Boahen: 2016 International Conference on Rebooting Computing
Neuromorphic Adaptive Edge-preserving Denoising Filter: IEEE Rebooting Computing 2017
A Spike-Timing Neuromorphic Architecture: IEEE Rebooting Computing 2017
A Comparison Between Single Purpose and Flexible Neuromorphic Processor Designs: IEEE Rebooting Computing 2017
Continuously Learning Neuromorphic Systems with High Biological Realism: IEEE Rebooting Computing 2017
Neuromorphic Mixed-Signal Circuitry for Asynchronous Pulse Processing Neuromorphic Mixed-Signal Circuitry for Asynchronous Pulse Processing - Peter Petre: 2016 International Conference on Rebooting Computing
Technology considerations for neuromorphic computing - David Mountain: 2016 International Conference on Rebooting Computing
An Energy-Efficient Mixed-Signal Neuron for Inherently Error Resilient Neuromorphic Systems - IEEE Rebooting Computing 2017
Energy Efficient Single Flux Quantum Based Neuromorphic Computing - IEEE Rebooting Computing 2017
A Unified Hardware/Software Co-Design Framework for Neuromorphic Computing Devices and Applications - IEEE Rebooting Computing 2017
Stochastic Single Flux Quantum Neuromorphic Computing using Magnetically Tunable Josephson Junctions - Stephen Russek: 2016 International Conference on Rebooting Computing
Connecting Silicon & Brain Neurons: Neuromorphic Computing - Stefano Vassanelli at INC 2019
"Introduction to Neuromorphic Computing - Insight and Challenges" (Rebooting Computing)
Conversion of Artificial Recurrent Neural Networks to Spiking Neural Networks for Low-power Neuromorphic Hardware - Emre Neftci: 2016 International Conference on Rebooting Computing
Episode 1 - Gert Cauwenberghs - Chip Chat Podcast
Learning with Memristive Neural Networks: Neuromorphic Computing - Joshua Yang at INC 2019
Neuromorphic computing with integrated photonics and superconductors - Jeffrey Shainline: 2016 International Conference on Rebooting Computing
Q&A with Karlheinz Meier: IEEE Rebooting Computing Podcast, Episode 19
Double Barrier Memristive Devices for Neuromorphic Computing - Martin Zeigler: 2016 International Conference on Rebooting Computing
Q&A with Gabriela Cruz Thompson: IEEE Rebooting Computing Podcast, Episode 28

IEEE-USA E-Books

  • III Technological and Scientific Impact

    None

  • Neuromorphic VLSI systems for visual information processing: drawbacks

    In this paper, the neuromorphic VLSI approach for visual processing and detection is presented. A brief history of neuromorphic vision systems is presented. The advantages and disadvantages of neuromorphic systems are highlighted and some of the major barriers towards realizing these systems are discussed. In particular, the implementation of early visual processing models using analogue VLSI is described and some of the general misconceptions are addressed.

  • Adaptation in a VLSI model of a neuron

    We have designed, fabricated, and tested an analog very large-scale integrated (VLSI) circuit model of a biological neuron that implements self-adaptation of its parameters. We show that the addition of this self-adaptation to our model neuron can facilitate: (1) single parameter control over a multiparameter system; (2) stability of the system to fluctuations in parameters; and (3) coordinated modulation of parameters to achieve a desired behavior.

  • Designing spiking neural networks

    The problem of design is the most important part of complex systems building. This is also true for spiking neural networks. In this paper, the next steps of SNN design are described: coding, selecting neuron model and learning algorithm, creating network architecture. Software and hardware solutions for simulating these networks are also discussed. We propose a range of evolution directions, future studies on every step of the design. Our methods are based on detailed analysis of existing solutions and needs.

  • A new computing rule for neuromorphic engineering

    Neuromorphic engineering has helped to build a brain-inspired intelligent paradigm based on VLSI, and to promise a new application space on smart devices. Throughout most of the state-of-the-art neuromorphic systems, including analog, digital, the mixed one, as well as some other memristor- based systems, the dominated computing rule in neuron is simply based on the linear-superposition operation of the excitatory and inhibitory pre-synaptic inputs. However, recent discoveries in neuroscience field reveal that the post-synaptic potential at the soma cannot be directly achieved by linearly adding up all the pre-synaptic inputs, which indicates the prevailing computing rule in current neuromorphic systems is not very biologically plausible. In this paper, we introduce a new computing rule in neuron block, which nonlinearly depends on the pre-synaptic inputs. Besides the superposition operation, the membrane potential is also related to the product item of the excitatory and inhibitory inputs. Furthermore, we design a heuristic circuit for the bio-plausible computing rule, which is compatible with the crossbar structure based systems. These results provide a new insight into the role of inhibitory signals in the brain, which is very helpful to explore more reliable computing principles in future neuromorphic devices.

  • Analog Logic Automata

    Analog logic circuits work on digital problems using an analog representation of the digital variables, relaxing the state space of the digital system from the vertices of a hypercube to the interior. This lets us gain speed, power, and accuracy over digital implementations. Logic automata are distributed, scalable and programmable digital computation media with local connections and logic operations. Here we propose analog logic automata (ALA), which relax binary constraints on logic automata states and introduce programmability into analog logic circuits. The localized interaction and scalability of the ALA provide a new way to do neuromorphic engineering, enabling systematic designs in a digital work flow. Low-power, biomedical, decoding and communication applications are described and a 3times3 ALA chip is prototyped, which works at 50 kHz, with a power consumption of 64 muW. With the chip configured as a programmable noise-locked loop (NLL), we obtain a bit error rate (BER) of 1E-7 at an SNR of -1.13 dB.

  • The brain and the computer

    Summary form only given. Exactly fifty years ago, when he published "The computer and the brain" in 1957, John von Neumann foresaw computer designers benefiting from basing their designs on the brain. Interest in this topic has been renewed by the convergence in properties of transistors and ion-channels (the brain's transistors). At ten nanometers, a transistor's channel becomes so narrow that an electron trapped by a dangling bond at the surface (an unavoidable atomistic defect) blocks electron flow. The current turns off and on at random, as trapping and detrapping occurs stochastically. Such stochastic behavior, which corrupts the deterministic on/off states computers rely on to perform binary arithmetic, is also displayed by ion-channels. At under a nanometer in size, an ion-channel's gate is agitated by thermal forces, opening and closing randomly. I will describe efforts in the neuromorphic engineering community to explore how the brain computes with stochastic devices by emulating an ion-channel's ionic current directly with a transistor's electronic current. While a present-day transistor, at a hundred- nanometers wide, corresponds to a small population of ion-channels, not a single ion-channel, this analog approach provides an extremely efficient method to simulate the brain while at the same time laying the groundwork for building brain-like computers out of next decade's nanotransis-tors. John von Neumann was prescient in anticipating that computer designers could profit by modeling features of the brain in their designs - even though he did not foresee the remarkable device-level convergence.

  • Real-time sensory information processing using the TrueNorth Neurosynaptic System

    Summary form only given. The IBM TrueNorth (TN) Neurosynaptic System, is a chip multi processor with a tightly coupled processor/memory architecture, that results in energy efficient neurocomputing and it is a significant milestone to over 30 years of neuromorphic engineering! It comprises of 4096 cores each core with 65K of local memory (6T SRAM)-synapses- and 256 arithmetic logic units - neurons-that operate on a unary number representation and compute by counting up to a maximum of 19 bits. The cores are event-driven using custom asynchronous and synchronous logic, and they are globally connected through an asynchronous packet switched mesh network on chip (NOC). The chip development board, includes a Zyng Xilinx FPGA that does the housekeeping and provides support for standard communication support through an Ethernet UDP interface. The asynchronous Addressed Event Representation (AER) in the NOC is al so exposed to the user for connection to AER based peripherals through a packet with bundled data full duplex interface. The unary data values represented on the system buses can take on a wide variety of spatial and temporal encoding schemes. Pulse density coding (the number of events Ne represents a number N), thermometer coding, time-slot encoding, and stochastic encoding are examples. Additional low level interfaces are available for communicating directly with the TrueNorth chip to aid programming and parameter setting. A hierarchical, compositional programming language, Corelet, is available to aid the development of TN applications. IBM provides support and a development system as well as “Compass” a scalable simulator. The software environment runs under standard Linux installations (Red Hat, CentOS and Ubuntu) and has standard interfaces to Matlab and to Caffe that is employed to train deep neural network models. The TN architecture can be interfaced using native AER to a number of bio-inspired sensory devices developed over many years of neuromorphic engineering (silicon retinas and silicon cochleas). In addition the architecture is well suited for implementing deep neural networks with many applications in computer vision, speech recognition and language processing. In a sensory information processing system architecture one desires both pattern processing in space and time to extract features in symbolic sub-spaces as well as natural language processing to provide contextual and semantic information in the form of priors. In this paper we discuss results from ongoing experimental work on real-time sensory information processing using the TN architecture in three different areas (i) spatial pattern processing -computer vision(ii) temporal pattern processing -speech processing and recognition(iii) natural language processing -word similarity-. A real-time demonstration will be done at ISCAS 2016 using the TN system and neuromorphic event based sensors for audition (silicon cochlea) and vision (silicon retina).

  • Consistent recovery of stimuli encoded with a neural ensemble

    We consider the problem of reconstructing finite energy stimuli from a finite number of contiguous spikes. The reconstructed signal satisfies a consistency condition: when passed through the same neuron, it triggers the same spike train as the original stimulus. The recovered stimulus has to also minimize a quadratic smoothness criterion. We show that under these conditions, the problem of recovery has a unique solution and provide an explicit reconstruction algorithm for stimuli encoded with a population of integrate- and-fire neurons. We demonstrate that the quality of reconstruction improves as the size of the population increases. Finally, we demonstrate the efficiency of our recovery method for an encoding circuit based on threshold spiking that arises in neuromorphic engineering.

  • Neuromorphic engineering: overview and potential

    Summary form only given. It is evident to even the most casual observer that the nervous systems of animals are able to accomplish feats that cannot be approached by our most powerful computing systems. Given the exponential increase in computing power over the last 45 years, our inability to rival the common housefly has become downright embarrassing. What is going on?.



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