Conferences related to Network-on-a-chip

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)

LASCAS aims at presenting a high-quality forum for researchers, designers, developers and graduate students to present the advances of their work on circuits and systems, amidst an international audience with experts from academia and industry all over the world. The LASCAS 2020 symposium will cover novel technical developments in all the areas of the Circuits and Systems Society, but focusing in the areas of biomedical and implantable devices and applications, low power integrated circuits, high speed communication interfaces and circuits and systems design for renewable energy applications.

  • 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)

    LASCAS is the Flagship Conference of IEEE's Circuits and Systems Society in Latin America. Since its inception and first edition in 2010, LASCAS aims at presenting a high-quality forum for researchers and graduate students to present the advances of their work, admits an international audience with experts from all over the world. This 10th edition will take place in Armenia, Quindío, Colombia

  • 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS)

    To present the most recent developments in the fields of electronic circuits and systems, including the whole range of applications.

  • 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS)

    Circuits and Systems

  • 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)

    The IEEE Latin American Symposium on Circuits and Systems (LASCAS) is the Latin American flagship conference and networking forum for worldwide engineers and researchers in the field of circuits and systems. While LASCAS is being organized by Latin American circuits & Systems community , it brings together worldwide researchers and engineers interested in theoretical, experimental, applications, or technology aspects of circuits & systems across a wide spectrum of scientific and technical fields:semiconductors, optoelectronics, sensors, VLSI, analog and digital circuits, RF circuits, biomedical circuits & systems, testing & reliability, multimedia and communications circuits & systems, among other topics.LASCAS will have a special emphasis on student activities, with grants for Latin American undergraduate students, and specific undergraduate student activities.

  • 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS 2015)

    The IEEE Latin American Symposium on Circuits and Systems (ISCAS) is Latin American flagship conference and networking forum for worldwide engineers and researchers in the field of circuits and systems. While LASCAS is being organized by Latin American circuits & Systems community , brings together worldwide researchers and engineers interested in theoretical, experimental, applications, or technology aspects of circuits & systems across a wide spectrum of scientific and technical fields:semiconductors, optoelectronics, sensors, VLSI, analog and digital circuits, neural network, biomedical circuits & systems, testing & reliability, multimedia and communications circuits & systems, among other topics.LASCAS will have a special emphasis on student activities, with grants for Latin American undergraduate students, and specific undergraduate student activities.

  • 2014 IEEE 5th Latin American Symposium on Circuits and Systems (LASCAS)

    The goal is to be the International Symposiumof IEEE Circuits and Systems in Latin America. The symposium will cover technical novelties andtutorial overviews on circuits and systems topics. It is the most important symposium on circuits and systems in Latin America having participants for all over the world.

  • 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)

    LASCAS 2013 is the International Symposium of IEEE Circuits and Systems in Latin America. LASCAS 2013 will include oral and poster, tutorials given by experts in state-of-the-art topics, and special sessions with the aim of complementing the regular program with topics of of relevant interest to the circuits and systems community.

  • 2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS)

    LASCAS's goal is to be the International Symposium of IEEE Circuits and Systems in Latin America. LASCAS 2012, sponsored by the IEEE Circuits and Systems Society and supported by INAOE, will be held in Playa del Carmen, Mexico. The scope of the conference is on topics related to circuits and systems such as: Analog and Digital Signal Processing, Biomedical Circuits and Systems, Multimedia Systems and Applications, Nanoelectronics, Cellular Neural Networks and Array Computing, Neural Systems and Applications, Circuits and Systems for Communications, Nonlinear Circuits and Systems, Computer-Aided Design, Power Systems and Power Electronic Circuits, Sensory Systems, Graph Theory and Computing, Visual Signal Processing and Communications, Life Science Systems and Applications, VLSI Systems and Applications, Electronic Testing, & Fault Tolerant Circuits.

  • 2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS)

    LASCAS 2011 will be the second version of the International Symposium of IEEE Circuits and Systems in Latin America. The program will include oral and poster presentations, complemented with special sessions to cover technical novelties and tutorial overviews on circuits and systems topics.

  • 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS)

    LASCAS2010 goal is to be the International Symposium of IEEE Circuits and Systems in Latin America. The LASCAS 2010 will include oral and poster; embedded tutorials given by experts in state-of-the-art topics; and special sessions, with the aim of complementing the regular program with topics of particular interest to the circuits and systems community.


2020 IEEE 29th International Symposium on Industrial Electronics (ISIE)

ISIE focuses on advancements in knowledge, new methods, and technologies relevant to industrial electronics, along with their applications and future developments.


2020 IEEE International Conference on Industrial Technology (ICIT)

ICIT focuses on industrial and manufacturing applications of electronics, controls, communications, instrumentation, and computational intelligence.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


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Periodicals related to Network-on-a-chip

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Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems Magazine, IEEE


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Most published Xplore authors for Network-on-a-chip

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Xplore Articles related to Network-on-a-chip

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Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Abstract form only given. This talk focuses on the functional testing of the NoC infrastructure. Herein, we are seeking for the integration of the test of interconnects and routers, at the lowest possible cost. Therefore, a manufacturing test strategy is proposed, that considers more realistic, logic level fault models, and attempts to fully cover faults that affect both the router ...


Reliable communication in systems on chips

Proceedings. 41st Design Automation Conference, 2004., 2004

System on Chip (SoC) design faces several challenges which are due to the extremely small nature of electronic devices and the consequent opportunity to realize multi-processing systems of extremely high complexity. To manage large scale design, SoCs are assembled out of complex standard parts, such programmable cores and memory arrays. Thus, the major design challenge is to provide correct and ...


Classical conditioning with pulsed integrated neural networks: circuits and system

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1998

In this paper, we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems, and we find that a biologically inspired approach using simple circuit structures is most likely to bring success. We develop a suitable learning algorithm-a continuous-time version of a temporal differential Hebbian learning algorithm for pulsed neural systems ...


A Modeling and exploration framework for interconnect network design in the nanometer era

2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009

As we approach serious scaling roadblocks in the next few process nodes, it is imperative to identify new emerging technologies that can complement or supplant CMOS in the future. We present an integrated cyclic approach to explore new interconnect technologies in the nanometer era for many core systems, where on-chip interconnects are jointly optimized at all the levels in the ...


Enabling Technology for On-Chip Interconnection Networks

First International Symposium on Networks-on-Chip (NOCS'07), 2007

As we enter the era of many-core processors and complex SoCs, on-chip interconnection networks play a dominant role in determining the performance, power, and cost of a system. These networks are critically dependent on a number of underlying technologies: channel, buffer, and switch circuits, router microarchitecture, flow-control and routing methods, and network topology. Too often on-chip networks are built in ...


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Educational Resources on Network-on-a-chip

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IEEE.tv Videos

No IEEE.tv Videos are currently tagged "Network-on-a-chip"

IEEE-USA E-Books

  • Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?

    Abstract form only given. This talk focuses on the functional testing of the NoC infrastructure. Herein, we are seeking for the integration of the test of interconnects and routers, at the lowest possible cost. Therefore, a manufacturing test strategy is proposed, that considers more realistic, logic level fault models, and attempts to fully cover faults that affect both the router logic and the communication channel wires. A functional-based approach is preferred, to reduce NoC re-design costs and to provide at-speed testing. However, scan and BISTbased approaches may be required to enhance both fault coverage and test application time.

  • Reliable communication in systems on chips

    System on Chip (SoC) design faces several challenges which are due to the extremely small nature of electronic devices and the consequent opportunity to realize multi-processing systems of extremely high complexity. To manage large scale design, SoCs are assembled out of complex standard parts, such programmable cores and memory arrays. Thus, the major design challenge is to provide correct and reliable operation of the interconnected components. Topdown correct component interconnection will become increasingly harder to succeed, because the interface features of components will also scale-up in complexity. New design methodologies will need to leverage component self- configuration and adaptation to the underlying communication fabric.

  • Classical conditioning with pulsed integrated neural networks: circuits and system

    In this paper, we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems, and we find that a biologically inspired approach using simple circuit structures is most likely to bring success. We develop a suitable learning algorithm-a continuous-time version of a temporal differential Hebbian learning algorithm for pulsed neural systems with nonlinear synapses-as well as circuits for the electronic implementation. Measurements from an experimental CMOS chip are presented. Finally, we use our test chip to solve simple classical conditioning tasks, thus verifying the design methodologies put forward in the paper.

  • A Modeling and exploration framework for interconnect network design in the nanometer era

    As we approach serious scaling roadblocks in the next few process nodes, it is imperative to identify new emerging technologies that can complement or supplant CMOS in the future. We present an integrated cyclic approach to explore new interconnect technologies in the nanometer era for many core systems, where on-chip interconnects are jointly optimized at all the levels in the design hierarchy to develop a complete interconnect solution - from interconnect technology to network topology.

  • Enabling Technology for On-Chip Interconnection Networks

    As we enter the era of many-core processors and complex SoCs, on-chip interconnection networks play a dominant role in determining the performance, power, and cost of a system. These networks are critically dependent on a number of underlying technologies: channel, buffer, and switch circuits, router microarchitecture, flow-control and routing methods, and network topology. Too often on-chip networks are built in a naive manner using a ring or mesh topology and standard cell methodology. Compared to this approach, optimized circuits can reduce power by an order of magnitude and an optimized topology can give an additional factor of two to three in area and power efficiency. This talk can explore key enabling technologies for on-chip networks giving a number of examples and identifying opportunities for future research

  • Energy Efficient NoC Design

    Summary form only given. Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we explore the delicate interplay between on-chip communication and power consumption. We move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects. We touch upon several energy optimization and management problems emerging in the design and tuning of on-chip interconnects. Our analysis show that energy-efficient on-chip communication is one of the cornerstones of system-level energy optimization

  • Design-for-Test of Asynchronous Networks-on-Chip

    Thanks to many advantages, asynchronous circuits have been used to solve the interconnect problems faced by system-on-chip (SoC) designers. Some asynchronous networks-on-chip (NoCs) architectures are proposed for the communication within SoCs, but lack methodology and support for manufacturing test to ensure these communication architectures work correctly. In this paper, we present an innovative asynchronous DfT architecture that allows to test the asynchronous communication network architectures, as well as the synchronous computing resources and the asynchronous/synchronous network interfaces on the asynchronous NoC-based SoCs. This asynchronous DfT architecture is implemented in quasi delay insensitive (QDI) asynchronous circuits and uses an area of about 20 * 8 Kgates in an asynchronous NoC-based SoC of 4.5 Mgates without memories

  • Challenges in ultra deep submicrometer high performance VLSI circuits

    Summary form only given. Fundamental trends specific to high speed, high complexity systems are reviewed, emphasizing many of the primary issues that constrain existing and future digital and mixed-signal integrated systems. These issues are discussed in terms of the evolving criteria that affect each aspect of the VLSI design and synthesis process. Attention is placed on distinguishing between local and global issues. Topics such as dual V/sub t/ CMOS circuits and on-chip interconnect noise, determined by the local nature of the circuit structures, are compared and contrasted with larger issues that focus on the global nature of VLSI-based systems such as synchronization styles and clock and power distribution networks.

  • Interconnect Considerations For High Performance Network on Chip Designs

    Network-on-a-Chip (NoC) is an emerging design style that involves building an on-chip network to link together the logic blocks on a complex system- on-a-chip. The result is any-to-any connectivity for complex data flows and, in early designs, a roughly 3X performance increase over legacy bus-based SoCs. The key design concept in a NoC is replacing the bus with an interconnect switch to link together the autonomous logic blocks. This design is an evolution of the globally asynchronous, locally synchronous (GALS) chip design. This presentation will discuss NoC architecture issues and the use of Fulcrum's Nexus on-chip interconnect technology as the central switching function in these devices. An elegant solution for this application, Fulcrum's Nexus is a 2.5Tbps non-blocking crossbar with up to 16 independent full-duplex ports, each capable of 160 Gbps of throughput. Nexus is designed using Fulcrum's patented circuit technology that gives the switch an extraordinarily low 3 ns latency, a modest power consumption level that is directly related to activity (300Gb/W) and an ultra small 2 mm × 2mm area. A Nexus-based GALS architecture provides the foundation for efficiently partitioning the massive amount of transistors available in next-generation, small geometry NoCs. It is estimated that these devices can support as many as two-dozen IP blocks, as compared to 6 or 8 in a typical 130 nm chip design. This will lead to logic blocks separated by very long wires.

  • Panel: Best ways to use billions of devices on a chip

    We all know that Moore's law is good for at least a few more generations of silicon process, and this will give rise to many integrated circuits having billions of transistors on them. The leading 45 nm processors being announced are getting close to a billion transistors as of 2007. But how can we best use these devices in the future? Integrating more and more features and functions onto SoCs may not be the optimal use for all of these billions of resources. Indeed, to even have a working device at 45, 32, 22 and 16 nm may require new architectures and new structures to be incorporated. Among the many ideas that can be advanced to best use the 'billions and billions served' are: (1) multicore and multiprocessor systems (2) yet more memory, to hold the embedded software and data required by multiprocessor architectures (3) more and more elaborate on-chip interconnect and network structures (4) redundant structures for defect tolerance (5) structures and architectures for dynamic error recovery (6) a variety of schemes to allow lower and lower power and energy consumption At the same time, billions of transistors on a chip will pose increasing challenges to our design methodologies, integration approaches and design tools. How can we best conceive of, architect, design, integrate, verify and manufacture such devices? This panel draws on several academic and industry experts who will discuss their views on the best things to integrate into future ICs, and the best ways to do that integration. It will give an excellent opportunity to the audience to challenge and discuss these ideas and to advocate their own views. As well as considering the 'best' ways to use these resources, the panel will also be a good opportunity to discuss the 'worst' ways to proceed. What architectural dead-ends should be avoided as we move through each silicon process generation?



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