Conferences related to Multivalued logic

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2020 IEEE International Conference on Robotics and Automation (ICRA)

The International Conference on Robotics and Automation (ICRA) is the IEEE Robotics and Automation Society’s biggest conference and one of the leading international forums for robotics researchers to present their work.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2019 Computing, Communications and IoT Applications (ComComAp)

ComComAp 2019 will target a wide spectrum of the state-of-the-art as well as emerging topics pertaining to computing, networks, wireless communications, and Internet of Things.

  • 2014 IEEE Computing, Communications and IT Applications Conference (ComComAp)

    Computers, Communications and IT Applications Conference (ComComAp 2014) will be held at Beijing, China, August 20-22, 2014. The conference is to address, explore and exchange information on the state-of-the-art in all types of computing systems, Communications, and networking as well as IT/Engineering applications. The main topics include but are not limited to (1)COMPUTING SYSTEMS and SOFTWARE- Intelligent Computing Systems - Scalable/Reconfigurable Computing- Interconnection Networks -Warehousing and Storage/ Data Mining and Searching- Computer Monitoring &Instrumentation - Performance Evaluation/ Modeling and Simulation- Systems Security and Trust - Embedded/Grid/Cluster/Multi-Core Architectures- Operating Systems and Compilers - Markup Languages and their Applications- Enterprise-based Technologies - Software Assurance/ Monitoring and Measurement(2)COMMUNICATIONS/NETWORKING AND INTERNET TECHNOLOGIES- Next Generation Internet - Wireless Networks/Systems- Next Generation/

  • 2013 Computing, Communications and IT Applications Conference (ComComAp)

    THE CONFERENCE WILL ADDRESS, EXPLORE AND EXCHANGE INFORMATION ON THE STATE-OF-THE-ART IN ALL TYPES OF COMPUTING SYSTEMS, COMMUNICATIONS AND NETWORKING AS WELL AS IT/ENGINEERING APPLICATIONS. PAPERS ON THE CURRENT STATE OF THE ART RESEARCH WORK ARE ENCOURAGED TO BE SUBMITTED.

  • 2012 Computing, Communications and Applications Conference (ComComAp)

    The conference is to address, explore and exchange information on the state-of-the-art in all types of computing systems, Communications, and networking as well as IT/Engineering applications.


2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)

Multiple-Valued Logic has many aspects. This yearly event attracts researchers in this area.

  • 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)

    The Conference will bring together researchers from computer science, engineering, mathematics, and further disciplines to discuss new developments and directions for future research in the area of multi-valued logic and related fields. Research papers, surveys, or tutorial papers on any subject in these areas are within the scope of the symposium.

  • 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)

    The symposium encompasses all aspects of multiple-valued logic and application.

  • 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)

    Multiple-valued logic (MVL) is the study of circuits, oftware, architectures, and systems in which information is carried by more than two values, or where information is presented in unconventional, i.e., non-binary-weighted ways. The scope of ISMVL covers a broad range of related topics, including fundamental algebra, theory and philosophy, logic synthesis, decision diagrams, reversible computing, quantum computing, microelectronic circuits, testing andverification, architectures, and modelling of novel devices, all within a multiple-valued framework.

  • 2015 IEEE International Symposium on Multiple-Valued Logic (ISMVL)

    Multiple-valued logic (MVL) is the study of circuits, software, architectures, and systems in which information is carried by more than two values, or where information is represented in unconventional, i.e., non-binary-weighted ways. The scope of ISMVL covers a broad range of related topics, including fundamental algebra, theory and philosophy, logic synthesis, decision diagrams, reversible computing, quantum computing, microelectronic circuits, testing and verification, architectures, and modelling of novel devices, all within a multiple-valued framework.

  • 2014 IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL)

    The aim of the conference is to present and disseminate knowledge in the areas related to multiple-valued logic, that is, to computing that is tolerant of imprecision, uncertainty, partial truth, and approximative reasoning. Specific topics include (but are not limited to):- Algebra and Formal Aspects- Automatic Test Pattern Generation- Automatic Reasoning- Boolean Satisfiability- Circuit/Device Implementation- Communication Systems- Computer Arithmetic- Data Mining- Fuzzy Systems and Soft Computing- Image Processing- Logic Design and Switching Theory- Logic Programming- Machine Learning and Robotics- Mathematical Fuzzy Logic- Nanotechnology- Philosophical Aspects- Quantum Computing- Quantum Cryptography- Reversible Computation- Signal Processing- Spectral Techniques- Verification

  • 2013 IEEE 43rd International Symposium on Multiple-Valued Logic (ISMVL)

    ISMVL is the principal annual meeting for the dissemination and discussion of research in multiple-valued logic and related areas. Topics cover all aspects of theory, implementation and application.

  • 2012 IEEE 42nd International Symposium on Multiple-Valued Logic (ISMVL)

    ISMVL is the principal annual meeting for the dissemination and discussion of research in multiple-valued logic and related areas. Topics cover all aspects of theory, implementation and application.

  • 2011 IEEE 41st International Symposium on Multiple-Valued Logic (ISMVL)

    areas of multiple-valued logic, including but not limited to: Algebra and Formal Aspects, ATPG and SAT, Automatic Reasoning, Circuit/Device Implementation, Communication Systems, Computer Arithmetic, Data Mining, Fuzzy Systems and Soft Computing, Image Processing, Logic Design and Switching Theory, Logic Programming Machine Learning and Robotics, Mathematical Fuzzy Logic, Nano Technology, Philosophical Aspects Quantum Computing, Signal Processing, Spectral Techniques, Verification.

  • 2010 40th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2010)

    The Multiple-Valued Logic Technical Committee of the IEEE Computer Society will hold its 40th annual symposium on May 26-28, 2010 in Casa Convalesc ncia, Barcelona, Spain. The event is sponsored by the IEEE Computer Society, and is organized by the Artificial Intelligence Research Institute of the Spanish National Research Council (IIIA-CSIC), the University of Barcelona, the Autonomous University of Barcelona, and the University of Lleida.

  • 2009 39th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2009)

    The area of multiple-valued logic is covered, including but not limited to: Algebra and Formal Aspects, Automatic Reasoning, Logic Programming, Philosophical Aspects, Fuzzy Logic and Soft Computing, Data Mining, Machine Learning and Robotics, Quantum Computing, Logic Design and Switching Theory, Test and Verification, Spectral Techniques, Circuit/Device Implementation, VLSI Architecture, VLSI Computing, System-on-Chip Technology, Nano Technology.

  • 2008 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008)

    The aim of ISMVL is to publish and disseminate knowledge in the field of multiple-valued logic and related areas. All aspects of MVL are considered at the symposium, ranging form algebra, formal aspects, and philosophy to logic design, verification, and circuit implementation.

  • 2007 37th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2007)

  • 2006 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006)

  • 2005 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005)


2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)

The IEEE International Midwest Symposium on Circuits and Systems is the oldest IEEE sponsored or co-sponsored conference in the area of analog and digital circuits and systems. Traditional lecture and interactive lecture/poster sessions cover virtually every area of electronic circuits and systems in all fields of interest to IEEE.


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Periodicals related to Multivalued logic

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Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


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Most published Xplore authors for Multivalued logic

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Xplore Articles related to Multivalued logic

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Fredkin gates as a basis for comparison of different logic design solutions

IEE Colloquium on Synthesis and Optimisation of Logic Systems, 1994

In this paper one particular gate is proposed which has the potential to be implemented optically. It has the advantage that, if necessary, it can perform conventional Boolean logic, but it can also perform alternative logics such as conservative logic, multi-valued logic and threshold logic. Since the same gate is used regardless of the logic, it is possible to make ...


IEE Colloquium on 'Synthesis and Optimisation of Logic Systems' (Digest No.1994/066)

IEE Colloquium on Synthesis and Optimisation of Logic Systems, 1994

None


A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors

IEEE Transactions on Electron Devices, 2002

A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si- based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTTs latching function and the MOSFETs switching function, the number of devices required for the D-FF circuit was greatly reduced to three from the thirty ...


Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007

This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder ...


Modelling of single electron ternary flip-flop using SIMON

2016 IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), 2016

Succeeding the Moore's law CMOS technology accumulated extreme device complexity with larger interconnects. But owing to physical scaling limitations CMOS technology itself is degrading the overall performance of binary logic ICs. This has augmented the urgency of Multi Valued Logic (MVL). A ternary logic or a three-valued logic is contemplated as the noblest radix of all assorted MVL formulates. The ...


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Educational Resources on Multivalued logic

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IEEE.tv Videos

Dynamic Logic Example
A perspective shift from Fuzzy logic to Neutrosophic Logic - Swati Aggarwal
Similarity and Fuzzy Logic in Cluster Analysis
Navigation and Control of Unmanned Vehicles: A Fuzzy Logic Perspective
The Hertzsprung-Russell Diagram: Introduction to Fuzzy Logic
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
Multi-Level Optimization for Large Fan-In Optical Logic Circuits - Takumi Egawa - ICRC 2018
The Sorites Paradox: Introduction to Fuzzy Logic
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic: IEEE Rebooting Computing 2017
Energy Efficiency of MRR-based BDD Circuits - Ozan Yakar - ICRC San Mateo, 2019
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
2013 IEEE Robert N. Noyce Medal
FinSAL: A Novel FinFET Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices - Himanshu Thapliyal: 2016 International Conference on Rebooting Computing
Hamid R Tizhoosh - Fuzzy Image Processing
Pt. 2: More Moore: Scaling of CMOS - An Chen - Industry Panel 2, IEEE Globecom, 2019
Provably-Correct Robot Control with LTLMoP, OMPL and ROS
Low-energy High-performance Computing based on Superconducting Technology
Plastic Logic's QUE E-Reader is Best of CES
Generating Stochastic Bits Using Tunable Quantum Systems - Erik Blair at INC 2019
IRDS: Lithography - Mark Neisser at INC 2019

IEEE-USA E-Books

  • Fredkin gates as a basis for comparison of different logic design solutions

    In this paper one particular gate is proposed which has the potential to be implemented optically. It has the advantage that, if necessary, it can perform conventional Boolean logic, but it can also perform alternative logics such as conservative logic, multi-valued logic and threshold logic. Since the same gate is used regardless of the logic, it is possible to make a comparison of the various logics, so that hopefully it can be shown that for specific applications Boolean logic may not always be the best solution.<<ETX>>

  • IEE Colloquium on 'Synthesis and Optimisation of Logic Systems' (Digest No.1994/066)

    None

  • A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors

    A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si- based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTTs latching function and the MOSFETs switching function, the number of devices required for the D-FF circuit was greatly reduced to three from the thirty required for the FET-only circuit.

  • Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

    This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder blocks. The circuit operates at a clock frequency of 1 Ghz. The supply voltage 1.0 Volt.

  • Modelling of single electron ternary flip-flop using SIMON

    Succeeding the Moore's law CMOS technology accumulated extreme device complexity with larger interconnects. But owing to physical scaling limitations CMOS technology itself is degrading the overall performance of binary logic ICs. This has augmented the urgency of Multi Valued Logic (MVL). A ternary logic or a three-valued logic is contemplated as the noblest radix of all assorted MVL formulates. The synthesis of ternary future ready logic circuits is itself a benchmark in device research arena. Yet there sustain ample research dearth to realize ternary hardware to meet the common needs of basic living. To cope up with such pivotal necessitates the authors here render a heuristic approach in developing ternary gates and flip-flops. Besides, Single Electronic technology is incorporated to further enhance the novel nature of the models in this paper. Initially the Single Electron ternary gates andflip-flops are simulated using Monte Carlo based SIMON 2.0 simulator and the simulation results exhibit a simple structure with less propagation delay and lower power consumption compared to conventional CMOS topology. Further it also ratify that such models are completely trustworthy and it accord perfectly with next generation computing having the merits of higher information storing capacity and thereby minimizing interconnections. Eventually more transistors can be cramped into the reduced chip dia in order to enhance the performance of SET MVL circuits.

  • Algebraic aspects of multiple-valued logic

    Some of the basic algebraic facts of multivalued logic are presented. The focus is on the results rather than on detailed proofs. Some of the results of completeness theory are also presented.<<ETX>>

  • A Redundant-Sensor-Based Fault Reasoning Technique for Multi-Sensors

    In magnetic bearing systems or other relative devices with multi-sensors which states are not easy to be monitored and tested, multi-valued logic algebra based on sequential variables is suggested to be utilized in the fault diagnosis of the multi-sensors. The states of sensors and devices are both discretized to be three logic values: normal, abnormal and a transition state between them. On the basis of proving several relative theorems that can reveal the relation between the states of the sensors and that of the devices, the experiment arrangement is discussed in detail when the state of a device is anyone of the three states respectively. All the completed experiments should be necessary and be without redundant ones. A novel redundant-sensor- based fault reasoning technique is presented to be used for fault diagnosis of multi-sensors according to the experiment results. The reasoning result shows that it is not in all the occasions that the state of every sensor can be determined. Fault diagnosis should be carried out early when there are not too many sensors with fault.

  • Fault analysis of the multiple valued logic using spectral method

    A method for detecting faults in Multiple Valued Logic (MVL) is proposed. The method depends on analyzing the spectral coefficients that are transformed for the Chrestenson spectral domain. The fault detecting conditions are derived for a single input stuck-at fault, multiple input s-a-f, a s-a-f at internal lines, and Min/Max bridging fault of the MVL. Fault detection is done based on the number of coefficients affected by a fault, and hence it is independent of the technology used for construction of networks and the types of fault. This method allows detection of the fault without the test vector, and minimize the memory size for storing test vectors and response data.

  • Multi-valued decoder based on resonant tunneling diodes in current tapping mode

    A multiple valued decoder based on RTDs is proposed and the functionality is verified via both simulation and experiment. The proposed circuit is simulated and tested with several single peaked RTD sections connected in series (stacked RTDs). The design uses current tapping techniques to switch on only one RTD section exclusively in order to create a single literal function. The number of RTD sections connected in series therefore determines the radix of signals used in the decoder.

  • Research on Temporal Multi-valued Dependency Cover

    As in traditional relational database, there also exists redundant data dependency in temporal database. Effective elimination of redundant data dependency is the foundation of further normalization for temporal databases. In order to eliminate redundant dependencies, cover of data dependency sets should be investigated. Coexist of multiple time granularities, temporal functional dependencies(TFDs) and temporal multi-valued dependencies(TMVDs) makes it more complicated to solve the cover problem of temporal database. To solve this problem, concepts of redundant temporal dependency, non-redundant temporal mixed cover and canonical temporal mixed dependency set are given. Corresponding cover algorithms are proposed which can solve the cover problem of mixed dependencies with both temporal functional dependencies and temporal multi-valued dependencies. It is the foundation for further normalization of temporal database.



Standards related to Multivalued logic

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Jobs related to Multivalued logic

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