1,050 resources related to Multithreading
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2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting
The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science
Multimedia technologies, systems and applications for both research and development of communications, circuits and systems, computer, and signal processing communities.
ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.
The 2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC 2020) will be held in Metro Toronto Convention Centre (MTCC), Toronto, Ontario, Canada. SMC 2020 is the flagship conference of the IEEE Systems, Man, and Cybernetics Society. It provides an international forum for researchers and practitioners to report most recent innovations and developments, summarize state-of-the-art, and exchange ideas and advances in all aspects of systems science and engineering, human machine systems, and cybernetics. Advances in these fields have increasing importance in the creation of intelligent environments involving technologies interacting with humans to provide an enriching experience and thereby improve quality of life. Papers related to the conference theme are solicited, including theories, methodologies, and emerging applications. Contributions to theory and practice, including but not limited to the following technical areas, are invited.
Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission
Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...
Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.
Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing
Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...
IBM Journal of Research and Development, 2013
As newer supercomputers continue to increase the number of threads, there is growing pressure on applications to exploit more of the available parallelism in their codes, including coarse-, medium-, and fine-grain parallelism. OpenMP™ is one of the dominant shared-memory programming models and is well suited for exploiting medium- and fine-grain parallelism. OpenMP research has focused on application tuning, compiler optimizations, ...
IEEE Distributed Systems Online, 2004
Proceedings of the Thirty-First Hawaii International Conference on System Sciences, 1998
Distributed shared memory systems have received considerable interest since the concept was originally proposed by Kai Li (1986). In such systems networks of workstations can be used to solve computationally intensive problems. Straightforward implementation of DSMs have suffered performance penalties. This has led to various relaxed memory consistency models that offer opportunities for optimizing performance of DSM systems. To further ...
22th International Conference on Architecture of Computing Systems 2009, 2009
The quest for high-performance has led to multi- and many-core systems. To push the performance of a single core to the limit, simultaneous multithreading (SMT) is used. SMT enables to fetch different instructions from different threads, hiding latencies in other threads. SMT also gives the opportunity to execute redundant threads (redundant multithreading, RMT) and thus to detect faults by comparing ...
2014 International Conference on Advances in Communication and Computing Technologies (ICACACT 2014), 2014
Very Long Instruction Word is an architectural breakthrough in DSP architecture that caters to the real time constraints and efficient algorithm implementation. This paper brings out various loopholes namely latency, underutilization of functional units, use of NOPs and constraints of cross path in register file accessing present in such architecture. This paper proposes a technique to reduce the delay slots ...
As newer supercomputers continue to increase the number of threads, there is growing pressure on applications to exploit more of the available parallelism in their codes, including coarse-, medium-, and fine-grain parallelism. OpenMP™ is one of the dominant shared-memory programming models and is well suited for exploiting medium- and fine-grain parallelism. OpenMP research has focused on application tuning, compiler optimizations, programming-model extensions, and porting to distributed-memory platforms; however, we have found that current algorithms used to implement basic OpenMP constructs have significant overheads and scale poorly. In this paper, we explore low- overhead, scalable algorithms for creating parallel regions and demonstrate reductions in overhead of up to a factor of 5 on an IBM Blue Gene®/Q node.
Distributed shared memory systems have received considerable interest since the concept was originally proposed by Kai Li (1986). In such systems networks of workstations can be used to solve computationally intensive problems. Straightforward implementation of DSMs have suffered performance penalties. This has led to various relaxed memory consistency models that offer opportunities for optimizing performance of DSM systems. To further improve the performance and eliminate false sharing, various DSM systems have tried numerous ad hoc techniques (e.g. combining several messages into a single message, permitting multiple writers to the same page). In a majority of these systems, the DSMs have been implemented on top of an existing OS kernel. This in itself has limited the performance as well as flexibility. The authors propose a new multithreaded-architecture for tolerating memory latencies. They also present some challenges to DSM system for supporting the multithreaded programming model and how the new architectures can aid in this regard.
The quest for high-performance has led to multi- and many-core systems. To push the performance of a single core to the limit, simultaneous multithreading (SMT) is used. SMT enables to fetch different instructions from different threads, hiding latencies in other threads. SMT also gives the opportunity to execute redundant threads (redundant multithreading, RMT) and thus to detect faults by comparing the results of both threads. The instruction fetch algorithm determines which instructions to fetch from which thread and therefore has great influence on processor performance. This work investigates the influence of different instruction fetch algorithms on the performance of an SMT processor by modeling it with Petri nets. Over the intrinsic results of a detailed processor simulation, our approach offers a generic evaluation. Furthermore, we distinguish between homogeneous (redundant execution, RMT) and inhomogeneous threads to determine the effects on the performance of each execution scheme with a dedicated instruction fetch algorithm. For inhomogeneous threads, the effect of instruction fetch algorithms can be confirmed, but not for homogeneous threads. Therefore, scheduling algorithms as simple as Round Robin can be recommended for redundant execution.
Very Long Instruction Word is an architectural breakthrough in DSP architecture that caters to the real time constraints and efficient algorithm implementation. This paper brings out various loopholes namely latency, underutilization of functional units, use of NOPs and constraints of cross path in register file accessing present in such architecture. This paper proposes a technique to reduce the delay slots present in the pipeline due to NOPs and hence obtain reduction in code size and reduced latency. With the available functional units, thread level parallelism is introduced to enhance existing instruction level parallelism, thus addressing the issue of under utilization of functional units. Aforementioned issues are dealt with by the use of multithreading - concept frequently associated with multi-core DSPs and RTOS. This paper reports a novel technique of introducing a programming discipline in assembly coding to emulate multithreading in a single core DSP without use of OS and reduction in the number of clock cycles required is observed. Code snippets implemented using Code Composer Studio for TMS320C6713 illustrate the concepts.
Aiming at the situation that monitoring for building equipments was separated and unable to be managed as a whole, the design and implement method of distribute three levers monitor and control network system were represented, a configuration of RS-485 bus and B/S, a data management and analysis method for building devices using VC++ multithreading, database Web accessing technique were also described. Database accessing method of realizing the equipments' concentrate monitor and control based on the technique of ADO developed. The system has functions such as of operation analyzing, data searching and editing, running curve and data statistics, printing of report forms, etc. According to the fact that the running data stream is great and uneven, statistics database and historical database were used to manage and store data, and it makes the system operate conveniently and efficiently.
Concurrency can be implemented in a Web server using synchronous and asynchronous mechanisms offered by the underlying operating system. Compared to the synchronous mechanisms, the asynchronous mechanisms are attractive because they provide the benefit of concurrency while alleviating much of the overhead and complexity of multithreading. The proactor pattern in middleware, which effectively encapsulates the asynchronous mechanisms supported by the operating system, can be used to implement a high performance Web server. In this paper, we present a queuing model of an asynchronous Web server implemented using the proactor pattern. We then describe a decomposition strategy to enable the application of the model in practical scenarios. We demonstrate the use of the model to guide configuration and provisioning decisions with several examples
In order to reduce the speed gap between today's processor and memory, many processors adopt multithreading technology, Intel IXP series Network Processor (NP) is such a typical kind. This paper takes IXP series Network Processor for example, first analyzes multithreading mechanism; then targeting on how to realize multi-thread synchronization, presents three design methods and a specific example which could illustrate the difference between these methods; at last does some experiments according to different design methods, from experiment results draws some conclusions which would be useful in designing applications based on multithreading NP, including producing as less constrains and context swaps as possible, making the program executing time be longer than the memory access latency at every stage and so on.
Power management is one of the most important issues in computer architecture today. Devices often operate on the edge of their thermal envelope and system designers must balance the power consumption of various system components in order to ensure safe operation. This paper proposes an adaptive scheduler for a multi-threaded SIMD processor which is able to trade performance for power consumption in order to stay within a given power budget. By moving threads between processor cores, the scheduler is able to create more opportunity for the use of aggressive power management techniques like clock gating. Evaluation shows the proposed algorithm enables more power savings than frequency scaling for various synthetic workloads.
This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high performance, high flexibility and ANSI-C support. WiMAX physical layer program has been implemented on the target architecture with the RTOS support. A semaphore based synchronization scheme is used to improve the task independence. The research lays a foundation for further exploration of multithreading on multiple target architectures.
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