Conferences related to Multiprocessor interconnection

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2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting

The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA)

Artificial Intelligence, Control and Systems, Cyber-physical Systems, Energy and Environment, Industrial Informatics and Computational Intelligence, Robotics, Network and Communication Technologies, Power Electronics, Signal and Information Processing


2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC)

OECC/PSC is one of the biggest worldwide conference on the optical communication, interconnects, and switching technologies. The scope includes optoelectronic components and devices, optical systems, optical interconnects, transmission, and networking.


2019 IEEE 15th International Conference on Control and Automation (ICCA)

The 15th IEEE International Conference on Control and Automation (IEEE ICCA 2019) will be held Tuesday through Friday, July 16-19, 2019, in Edinburgh, Scotland. The conference is jointly organized by IEEE Control Systems Chapter, Singapore, and IEEE Control Chapter for United Kingdom and Ireland. It is technically sponsored by IEEE Control Systems Society. It aims to create a forum for scientists and practising engineers throughout the world to present the latest research findings and ideas in the areas of control and automation, and possible contributions toward sustainable development and environment preservation. The conference is featured with the Best Paper Award and the Best Student Paper Award.


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Periodicals related to Multiprocessor interconnection

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Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


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Most published Xplore authors for Multiprocessor interconnection

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Xplore Articles related to Multiprocessor interconnection

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Decomposition of total exchange for multidimensional interconnects

Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing, 1996

Total exchange is an important collective communication problem in multiprocessor interconnection networks. It involves the dissemination of distinct messages from every node to every other node. We present a novel theory for solving the problem in any multidimensional (cartesian product) network. We construct a general algorithm and provide optimality conditions. It is seen that many of the popular topologies, including ...


A fast and low cost self-routing permutation network

IEEE Transactions on Computers, 1998

In this paper, we present a new implementation of the fast VLSI-efficient self-routing N/spl times/N permutation network proposed by Cam and Fortes, which requires only about half as much hardware and has a lower latency. Cam and Fortes' implementation uses Cormen and Leiserson's hyperconcentrators, which can route only active inputs. The reduction in hardware is achieved by modifying Cormen and ...


Building Block Concept for Static Connected MIMDs: Development of Building Block Modules

The 24th Southeastern Symposium on System Theory and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design, 1992

Multiprocessor interconnection topologies usually implement specific algorithms that can map various types of connections, i.e. binary tree, N-Cube, etc. However, the research conducted uncovered the lack of uniformity incorporated in network topology designs. In other words, the lack of uniformity reduced the capability for expandability within a topology. Within a mesh type connectivity pattern, the topology is very scalable and ...


Design and analysis of cache coherent multistage interconnection networks

IEEE Transactions on Computers, 1993

A directory of state information is introduced into a multistage interconnection network (MIN) switch, and a multiple copy cache coherence protocol is developed. It is shown that the protocol is better than a single copy protocol on this MIN with directories (MIND) scheme. A network called the multistage bus network (MBN), which introduces a bus and multiple snoopers into the ...


Topological properties and optimal routing algorithms for three dimensional hexagonal networks

Proceedings Fourth International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, 2000

The paper presents a convenient addressing scheme on 2D hexagonal meshes. It helps to derive simple and optimal routing and one-to-all broadcasting algorithms. We also show the existence of a Hamiltonian cycle that yields a ring embedding. We define 3D hexagonal graph as a generalization of the triangular plane tessellation, and consider it as a multiprocessor interconnection network. Some of ...


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Educational Resources on Multiprocessor interconnection

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IEEE-USA E-Books

  • Decomposition of total exchange for multidimensional interconnects

    Total exchange is an important collective communication problem in multiprocessor interconnection networks. It involves the dissemination of distinct messages from every node to every other node. We present a novel theory for solving the problem in any multidimensional (cartesian product) network. We construct a general algorithm and provide optimality conditions. It is seen that many of the popular topologies, including hypercubes, k-ary n-cubes and general tori satisfy these conditions. The results we present here apply to the single-port model.

  • A fast and low cost self-routing permutation network

    In this paper, we present a new implementation of the fast VLSI-efficient self-routing N/spl times/N permutation network proposed by Cam and Fortes, which requires only about half as much hardware and has a lower latency. Cam and Fortes' implementation uses Cormen and Leiserson's hyperconcentrators, which can route only active inputs. The reduction in hardware is achieved by modifying Cormen and Leiserson's hyperconcentrator to route active, as well as inactive, inputs to the output. This modification allows us to reduce the number of hyperconcentrators needed in the permutation network by 50 percent and eliminate the interstage interconnection networks, making the permutation network faster by log/sub 2/N bits.

  • Building Block Concept for Static Connected MIMDs: Development of Building Block Modules

    Multiprocessor interconnection topologies usually implement specific algorithms that can map various types of connections, i.e. binary tree, N-Cube, etc. However, the research conducted uncovered the lack of uniformity incorporated in network topology designs. In other words, the lack of uniformity reduced the capability for expandability within a topology. Within a mesh type connectivity pattern, the topology is very scalable and is truly uniform, but nonetheless there is a problem with the structure due to topology-inherent communication delays. Therefore, having identified the problem, the approach taken to attempt a solution was to somehow realize the possibility of developing a network topology (TM-Cube) that is purely uniform and still performs at maximum efficiency. Comparison will be based on our assumed reference model, the N-Cube.

  • Design and analysis of cache coherent multistage interconnection networks

    A directory of state information is introduced into a multistage interconnection network (MIN) switch, and a multiple copy cache coherence protocol is developed. It is shown that the protocol is better than a single copy protocol on this MIN with directories (MIND) scheme. A network called the multistage bus network (MBN), which introduces a bus and multiple snoopers into the switches of a MIN, is presented. The snooping buses form multiple trees with the memories at the roots and the processors at the leaves. Each switch contains directories to hold state information on the shared blocks that is used to filter the coherence traffic from one level to another. The shared requests pass through the directories, whereas the private requests pass directly from the bus in one level to the bus in the next level. Analytical and simulation models for these multistage cache coherent architectures are developed. Both the MIND and the MBN schemes are studied with a simple multiple copy protocol. The results show that the MBN scheme performs better than the MIND or conventional scheme.<<ETX>>

  • Topological properties and optimal routing algorithms for three dimensional hexagonal networks

    The paper presents a convenient addressing scheme on 2D hexagonal meshes. It helps to derive simple and optimal routing and one-to-all broadcasting algorithms. We also show the existence of a Hamiltonian cycle that yields a ring embedding. We define 3D hexagonal graph as a generalization of the triangular plane tessellation, and consider it as a multiprocessor interconnection network. Some of its topological properties are studied. These properties are better than the well known multidimensional square mesh. A simple and optimal routing algorithm is also presented.

  • High-performance self-routing algorithm for multiprocessor systems with shuffle interconnections

    This paper proposes a routing algorithm for the interconnection of multiple processors based on the shortest-path and deflection-routing principles. The routing algorithm, named SPDRA (Shortest Path and Deflection Routing Algorithm), is applied to multiprocessor systems with a single-stage shuffle physical topology. SPDRA is general-purpose, as opposed to the majority of routing algorithms for multiprocessor systems which are optimized for particular traffic patterns generated by a restricted class of parallel algorithms. The general-purpose nature of SPDRA allows perfomance comparisons with a wide class of routing algorithms for multiprocessor systems that, similar to the single-stage shuffle physical topology, have a fixed node-to- processor ratio. The paper compares SPDRA with hypercube algorithms for bidimensional meshes and torus physical topologies, routing algorithms for hierarchical tridimensional tori, and algorithms for routing permutations in shuffle networks, which constitute the most widely accepted approaches for multiprocessor interconnection. SPDRA exhibits a performance advantage for a broad range of network sizes and, in general, the performance advantage grows as the number of processors increases. However, this paper compares the SPDRA algorithm against a limited set of multiprocessor systems and does not demonstrate a general superiority of SPDRA over all systems with a fixed node- to-processor ratio and, especially, with a growing node-to-processor ratio, such as multistage networks.

  • On the blocking performance of EGS networks under multicast traffic

    Extended generalized shuffle (EGS) networks are a wide class of interconnection networks introduced by Richards (1993). In this work, we study the blocking performance of EGS networks under point-to-multipoint traffic. Two new routing algorithms for multicast connections in EGS networks are defined, and a theorem proving that these algorithms construct minimum-cost connection trees is enclosed. Simulation results show that the blocking performance of EGS networks under multicast traffic is much better than that of three-stage Clos networks of equal complexity.

  • Quality of service routing algorithm in the torusbased network on chip

    Network on chip (NoC) is an emerging area and recognized as the future methodology for chip design. Provision of QoS in network on chip is a challenging problem and receives much attention recently. A QoS routing scheme is proposed to support various traffic with different QoS requirements in the interconnection networks of NoC. Specifically, three distributed QoS routing algorithms are developed based on different blocking handling methods. The algorithms use local information and are proven to be deadlock free and livelock free. Various strategies to handle blocking are utilized to lower the call failure rate. Simulations are carried on 3D torus topology. The results show that the proposed algorithms increase the network capacity by 30-40% (compared with the dimension order algorithm) and by 20-30% (compared with Duato's algorithm).

  • Routing in General Incomplete Star Interconnection Network

    In this paper, we propose a new routing algorithm for the general incomplete star interconnection network (GISN). The diameter of GISN is shown to be bounded by 3.5n-5. This improves on a 4n-7 routing algorithm described earlier in Shi Yutao, et al., (2002). We also prove that the diameter of GISN is more than or equals to lfloor3(n-2)/2rfloor+1.

  • Super Strongly Perfect ness of Prism and Rook's Networks

    A Graph G is Super Strongly Perfect Graph if every induced sub graph H of G possesses a minimal dominating set that meets all the maximal complete sub graphs of H. In this paper we have characterized the structure of super strongly perfect graphs in Prism and Rook's Networks. Along with this characterization, we have investigated the Super Strongly Perfect ness in Prism and Rook's Networks. Also we have given the relationship between diameter, domination and co-domination numbers of Prism Network.



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