Conferences related to Multiplying circuits

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2019 24th Asia and South Pacific Design Automation Conference (ASP-DAC)

ASP-DAC 2019 is the twenty-second annual international conference on VLSI design automation in Asia and South Pacific region, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.


2019 44th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz)

Science, technology and applications spanning the millimeter-waves, terahertz and infrared spectral regions


2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

This is a set of five conferences with a focus on wireless components, applications and systems that affect both now and our future lifestyle. The main niche of these conferences is to bring together technologists, circuit designers, system designers and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems. This is also an area where today's design compromises can trigger tomorrow's advanced technologies, where dreams can become a reality.


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Periodicals related to Multiplying circuits

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


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Most published Xplore authors for Multiplying circuits

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Xplore Articles related to Multiplying circuits

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Design of an analogue subthreshold multiplier suitable for implementing an artificial neural network

IEE Proceedings G - Circuits, Devices and Systems, 1992

Describes work undertaken as a final-year undergraduate project and considers the design of an analogue VLSI implementation of the multi-layer perceptron artificial neural network. The network is principally composed of multipliers, and therefore the design effort concentrated on the development of a space- efficient multiplier. The circuit exploits the subthreshold region of operation of a MOSFET and it was necessary ...


Bit-serial modular multiplier

Electronics Letters, 1989

A bit-serial modular multiplier is presented which uses a table look-up method to perform modular reduction. Since the clock frequency is independent of word length this design is most useful when dealing with large integers, and is required by many modern cryptographic systems.<<ETX>>


VLSI design for diminished-1 multiplication of integers modulo a Fermat number

IEE Proceedings E - Computers and Digital Techniques, 1988

The paper presents two new multiplication algorithms for Fermat number transforms which have improved speed, and in which both the algorithm and the hardware circuitry are simplified. These advantages arise from the properties of the diminished-1 addition, which allow the need to generate a rather complicated initial state to be eliminated. Also, a number represented in the diminished-1 number scheme ...


CMOS four-quadrant multiplier using bias offset crosscoupled pairs

Electronics Letters, 1993

A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that a for a power supply of +or-5 V, the linearity error is less than 1% over a +or-2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.<<ETX>>


Compact, low-power, analogue building blocks derived from MOSFETs translinear loops

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

Three useful analogue building blocks based on the translinear principle applied to MOS transistors operated in weak-inversion, are presented. A four- quadrant parametric current amplifier, coming in both a global biasing and local biasing flavor, and a two-quadrant current divider are derived from a basic translinear loop composed by 4 transistors. The resulting circuits are very compact and precise. Simulation ...


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Educational Resources on Multiplying circuits

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IEEE-USA E-Books

  • Design of an analogue subthreshold multiplier suitable for implementing an artificial neural network

    Describes work undertaken as a final-year undergraduate project and considers the design of an analogue VLSI implementation of the multi-layer perceptron artificial neural network. The network is principally composed of multipliers, and therefore the design effort concentrated on the development of a space- efficient multiplier. The circuit exploits the subthreshold region of operation of a MOSFET and it was necessary to examine in detail the modelling of this region of operation. In the course of the work, design tools made available under the ECAD initiative were used; in particular, the circuit simulator HSPICE was used for parameter extraction, in an unconventional way, to great advantage.<<ETX>>

  • Bit-serial modular multiplier

    A bit-serial modular multiplier is presented which uses a table look-up method to perform modular reduction. Since the clock frequency is independent of word length this design is most useful when dealing with large integers, and is required by many modern cryptographic systems.<<ETX>>

  • VLSI design for diminished-1 multiplication of integers modulo a Fermat number

    The paper presents two new multiplication algorithms for Fermat number transforms which have improved speed, and in which both the algorithm and the hardware circuitry are simplified. These advantages arise from the properties of the diminished-1 addition, which allow the need to generate a rather complicated initial state to be eliminated. Also, a number represented in the diminished-1 number scheme is always one less than its normal binary value, thus enabling the translation step to be avoided by considering the least significant bit (LSB) of the multiplier as a special case having the value LSB+1. One of the algorithms has already been realised using NMOS VLSI technology. The circuit has been designed hierarchically and uses regular structures and is expandable, which makes it very suitable for VLSI implementation. A logic diagram for realisation of the second algorithm is also given and this it to be implemented using CMOS technology. It is estimated that the time taken to complete modulo F/sub 4/ multiplication would be 1 mu s.<>

  • CMOS four-quadrant multiplier using bias offset crosscoupled pairs

    A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that a for a power supply of +or-5 V, the linearity error is less than 1% over a +or-2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.<<ETX>>

  • Compact, low-power, analogue building blocks derived from MOSFETs translinear loops

    Three useful analogue building blocks based on the translinear principle applied to MOS transistors operated in weak-inversion, are presented. A four- quadrant parametric current amplifier, coming in both a global biasing and local biasing flavor, and a two-quadrant current divider are derived from a basic translinear loop composed by 4 transistors. The resulting circuits are very compact and precise. Simulation results for all the circuits and measurements of a realized prototype of a two-quadrant current amplifier are provided. Low-voltage, low-power performances with input currents ranging over three decades and relative errors smaller than 3% are achieved.

  • Serial-parallel multiplier for two's complement numbers

    A serial-parallel multiplier for two's complement numbers is proposed. Based on an efficient two's complement multiplication algorithm, the proposed multiplier is composed of modularised logic blocks and locally interconnected signal lines, which is suitable for VLSI implementation. It requires 2n+1 cycles to obtain a complete product, which is the same delay as in the unsigned scheme except that one XOR gate delay is added to each cycle.<<ETX>>

  • Carry delayed save adders for computing the product A.B modulo N in log/sub 2/ N steps

    The design of a new modular multiplier which uses carry delayed save adders is presented. The system makes use of the techniques of sign estimation and digital division from the right in order to produce the product in n steps. The inputs to the device can be in carry save, delayed save or standard binary and the output is produced as a delayed save integer. This means that the system is ideal for use in situations where the product produced by the previous operation is then fed back to be re-multiplied, e.g. repeated squaring and exponentiation.<<ETX>>

  • Low-voltage, four-quadrant, analogue CMOS multiplier

    A CMOS four quadrant analogue multiplier that can operate from a supply voltage of 1.5 V is described. The multiplier requires two linear transconductors whose input transistors are operated in their linear region. Simulation results indicate that the nonlinearity can be kept below 0.8%, across the entire differential input voltage range of +or-400 mV.<<ETX>>

  • Evaluation of Booth encoding techniques for parallel multiplier implementation

    Although generally used in parallel multipliers, Booth encoding is shown to be obsolete due to the improvements in bit compression trees. It was found that a simple row of 4:2 compressors reduces the number of partial products to one half, which is the essential function of the Booth encoding technique. With a single row of 4:2 compressors this reduction is achieved in less time and with fewer gates used.<<ETX>>

  • New architecture for parallel multipliers

    An architecture for parallel multipliers, based on 2 bit full adders, is proposed. Multipliers built in this way possess the same structure as previously published five-counter multipliers, but with fewer cells and a reduction of one stage. The architecture is particularly suited to nFET complex block pipelined dynamic logic, and the 2 bit adder cell appears to be more efficient than the five-counter cell.<<ETX>>



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