Memory architecture

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Memory architecture describes the methods used to implement electronic computer data storage in a manner that is a combination of the fastest, most reliable, most durable, and least expensive way to store and retrieve information. (Wikipedia.org)






Conferences related to Memory architecture

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2020, the 27th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


2020 IEEE International Conference on Multimedia and Expo (ICME)

Multimedia technologies, systems and applications for both research and development of communications, circuits and systems, computer, and signal processing communities.

  • 2019 IEEE International Conference on Multimedia and Expo (ICME)

    speech, audio, image, video, text and new sensor signal processingsignal processing for media integration3D imaging, visualization and animationvirtual reality and augmented realitymulti-modal multimedia computing systems and human-machine interactionmultimedia communications and networkingmedia content analysis and searchmultimedia quality assessmentmultimedia security and content protectionmultimedia applications and servicesmultimedia standards and related issues

  • 2018 IEEE International Conference on Multimedia and Expo (ICME)

    The IEEE International Conference on Multimedia & Expo (ICME) has been the flagship multimedia conference sponsored by four IEEE societies since 2000. It serves as a forum to promote the exchange of the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities. ICME also features an Exposition of multimedia products and prototypes.

  • 2017 IEEE International Conference on Multimedia and Expo (ICME)

    Topics of interest include, but are not limited to: – Speech, audio, image, video, text and new sensor signal processing – Signal processing for media integration – 3D visualization and animation – 3D imaging and 3DTV – Virtual reality and augmented reality – Multi-modal multimedia computing systems and human-machine interaction – Multimedia communications and networking – Media content analysis – Multimedia quality assessment – Multimedia security and content protection – Multimedia databases and digital libraries – Multimedia applications and services – Multimedia standards and related issues

  • 2016 IEEE International Conference on Multimedia and Expo (ICME)

    Topics of interest include, but are not limited to:- Speech, audio, image, video, text and new sensor signal processing- Signal processing for media integration- 3D visualization and animation- 3D imaging and 3DTV- Virtual reality and augmented reality- Multi-modal multimedia computing systems and human-machine interaction- Multimedia communications and networking- Media content analysis- Multimedia quality assessment- Multimedia security and content protection- Multimedia databases and digital libraries- Multimedia applications and services- Multimedia standards and related issues

  • 2015 IEEE International Conference on Multimedia and Expo (ICME)

    With around 1000 submissions and 500 participants each year, the IEEE International Conference on Multimedia & Expo (ICME) has been the flagship multimedia conference sponsored by four IEEE societies since 2000. It serves as a forum to promote the exchange of the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities.

  • 2014 IEEE International Conference on Multimedia and Expo (ICME)

    The IEEE International Conference on Multimedia & Expo (ICME) has been the flagship multimedia conference sponsored by four IEEE societies since 2000. It serves as a forum to promote the exchange of the latest advances in multimedia technologies, systems, and applications. In 2014, an Exposition of multimedia products, prototypes and animations will be held in conjunction with the conference.Topics of interest include, but are not limited to:

  • 2013 IEEE International Conference on Multimedia and Expo (ICME)

    To promote the exchange of the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities.

  • 2012 IEEE International Conference on Multimedia and Expo (ICME)

    IEEE International Conference on Multimedia & Expo (ICME) has been the flagship multimedia conference sponsored by four IEEE Societies. It exchanges the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities.

  • 2011 IEEE International Conference on Multimedia and Expo (ICME)

    Speech, audio, image, video, text processing Signal processing for media integration 3D visualization, animation and virtual reality Multi-modal multimedia computing systems and human-machine interaction Multimedia communications and networking Multimedia security and privacy Multimedia databases and digital libraries Multimedia applications and services Media content analysis and search Hardware and software for multimedia systems Multimedia standards and related issues Multimedia qu

  • 2010 IEEE International Conference on Multimedia and Expo (ICME)

    A flagship multimedia conference sponsored by four IEEE societies, ICME serves as a forum to promote the exchange of the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities.

  • 2009 IEEE International Conference on Multimedia and Expo (ICME)

    IEEE International Conference on Multimedia & Expo is a major annual international conference with the objective of bringing together researchers, developers, and practitioners from academia and industry working in all areas of multimedia. ICME serves as a forum for the dissemination of state-of-the-art research, development, and implementations of multimedia systems, technologies and applications.

  • 2008 IEEE International Conference on Multimedia and Expo (ICME)

    IEEE International Conference on Multimedia & Expo is a major annual international conference with the objective of bringing together researchers, developers, and practitioners from academia and industry working in all areas of multimedia. ICME serves as a forum for the dissemination of state-of-the-art research, development, and implementations of multimedia systems, technologies and applications.

  • 2007 IEEE International Conference on Multimedia and Expo (ICME)

  • 2006 IEEE International Conference on Multimedia and Expo (ICME)

  • 2005 IEEE International Conference on Multimedia and Expo (ICME)

  • 2004 IEEE International Conference on Multimedia and Expo (ICME)

  • 2003 IEEE International Conference on Multimedia and Expo (ICME)

  • 2002 IEEE International Conference on Multimedia and Expo (ICME)

  • 2001 IEEE International Conference on Multimedia and Expo (ICME)

  • 2000 IEEE International Conference on Multimedia and Expo (ICME)


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


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Periodicals related to Memory architecture

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


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Most published Xplore authors for Memory architecture

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Xplore Articles related to Memory architecture

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IEE Colloquium on 'Parallel Techniques for Information Retrieval' (Digest No.54)

IEE Colloquium on Parallel Techniques for Information Retrieval, 1989

None


Correction

IEEE Solid-State Circuits Magazine, 2016

In the article "Memory Interfaces: Past, Present, and Future", Figure 16 was incorrect due to a production error. The corrected figure is displayed.


X-series approach to high density 128K and high speed 32K EPROMs

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1980

None


A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

2010 IEEE International Memory Workshop, 2010

Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (~20 nm) and poly channel thickness (~10nm) can not be scaled further. Among them VG may have the best X-direction scalability to F~2X nm node, ...


Efficient VLSI implementation of radix-8 FFT algorithm

1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368), 1999

High-radix Cooley-Turkey FFT algorithms have obvious advantages: less multiplications and reduced memory accesses so power consumption can be reduced. However, the disadvantages are that traditional direct mapping implementation of high-radix butterfly element will required more complex multipliers and thus large silicon area will be consumed. In this paper, we proposed an efficient approach to realize the high radix butterfly process ...


More Xplore Articles

Educational Resources on Memory architecture

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IEEE.tv Videos

Future of Computing: Memory/Storage - Steve Pawlowski - ICRC San Mateo, 2019
Memory Centric Artificial Intelligence - Damien Querlioz at INC 2019
Rebooting Memory Architecture - Wen-mei Hwu at INC 2019
Computing in the Cambrian Era - ICRC 2018 Plenary, Paolo Faraboschi
IRDS: Beyond CMOS & Emerging Research Materials - Shamik Das at INC 2019
Rebooting Computing Panel - Stan Williams: 2016 Technology Time Machine
High-Bandwidth Memory Interface Design
The Superstrider Architecture: Integrating Logic and Memory towards non-von Neumann Computing: IEEE Rebooting Computing 2017
Molecular Cellular Networks: A Non von Neumann Architecture for Molecular Electronics - Craig Lent: 2016 International Conference on Rebooting Computing
Stochastic Sampling Machine for Bayesian Inference - Raphael Frisch at INC 2019
Devices: Next 20 Years Panel - Mustafa Badaroglu at INC 2019
FPGA demonstrator of a Programmable ML Inference Accelerator - Martin Foltin - ICRC San Mateo, 2019
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip - Anirudh Jain - ICRC 2018
Pt. 2: More Moore: Scaling of CMOS - An Chen - Industry Panel 2, IEEE Globecom, 2019
Future Computing Systems (FCS) to Support Understanding Capability - Sergey Serebryakov - ICRC San Mateo, 2019
A Closer Look at NFV Execution Models - Zhi-Li Zhang - IEEE Sarnoff Symposium, 2019
Architecture: Next 20 Years Panel - Kirk Bresniker at INC 2019
IRDS: More Moore Outbrief - Mustafa Badaroglu at INC 2019
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing

IEEE-USA E-Books

  • IEE Colloquium on 'Parallel Techniques for Information Retrieval' (Digest No.54)

    None

  • Correction

    In the article "Memory Interfaces: Past, Present, and Future", Figure 16 was incorrect due to a production error. The corrected figure is displayed.

  • X-series approach to high density 128K and high speed 32K EPROMs

    None

  • A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

    Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (~20 nm) and poly channel thickness (~10nm) can not be scaled further. Among them VG may have the best X-direction scalability to F~2X nm node, and no penalty of increasing Z layer number since the channel current flows horizontally. We propose a buried-channel junction-free NAND to improve the read current for all 3D NAND arrays and our simulation results well support this structure. For the first time, “Z-interference” in 3D NAND Flash is examined and it indicates a new Z-direction scaling limitation. The present work is of crucial importance in understanding various 3D NAND Flash approaches.

  • Efficient VLSI implementation of radix-8 FFT algorithm

    High-radix Cooley-Turkey FFT algorithms have obvious advantages: less multiplications and reduced memory accesses so power consumption can be reduced. However, the disadvantages are that traditional direct mapping implementation of high-radix butterfly element will required more complex multipliers and thus large silicon area will be consumed. In this paper, we proposed an efficient approach to realize the high radix butterfly process element. This approach employed pipelining techniques to cascade the paralleled multipliers and thus fewer complex multipliers are utilized to realize the radix-r butterfly element. This approach can achieve a good trade- off between speed and area in the design of high radix butterfly element.

  • Memory hierarchy management for iterative graph structures

    The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications, this results in a wide disparity between sustained and peak achievable speed. Applications need to be tuned to processor and memory system architectures for cache locality, memory layout and data prefetch and reuse. In this paper we investigate optimizations for unstructured iterative applications in which the computational structure remains static or changes only slightly through iterations. Our methods reorganize the data elements to obtain better memory system performance without modifying code fragments. Our experimental results show that the overall time can be reduced significantly using our optimizations. Further, the overhead of our methods is small enough that they are applicable even if the computational structure does nor substantially change for tens of iterations.

  • A two-level on-chip memory for video signal processor

    The authors propose an on-chip memory architecture for video signal processor (VSP). According to the nature of different data locality in video source coding applications, the memory adopts a novel two-level scheme for making trade-off between capacity and flexibility. The upper level, Memory A, provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level, Memory B, provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. They have designed a prototype memory using 1.2- mu m SPDM SRAM technology.<<ETX>>

  • An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array

    This paper describes a novel architecture for a content-addressable memory core which is intended to be included in a Field-Programmable Gate Array or an Embedded Programmable Logic Core. Compared to a standard content-addressable memory, our architecture allows for arbitrary data and tag widths; this flexibility is vital in FPGA applications, since the size of the data and tag fields are not known when the FPGA is manufactured.

  • Latency Analyses of CC-NUMA and CC-COMA Rings

    This paper focuses comparative performance modeling and evaluation of CC-NUMA and CC-COMA on a hierarchical ring shared-memory architecture. Intensive performance measurements of the two models have been conducted on the KSR-1. The experimental results support the analytical models, and present practical observations and comparisons of the two cache coherence memory systems. Our analytical and experimental results show that a CC-COMA system balances the work load well. However the overhead of frequent data movement may match the gains obtained from improving load balance. Although a CC-NUMA system may not automatically balance the load at the system level, it provides an option for a user to explicitly handle data locality for a possible performance improvement.

  • Dual Run-time Environments for Dual Data Memory Bank Architecture

    Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to manipulate dual run-time environment. The run-time environment for dual data memory banks requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. Unfortunately, several existing compilers use only single stack or fully static dual run-time stack. The former cannot utilize dual data memory banks, and the latter waste run-time memory. Therefore, we provide dual run- time environment based on stacks in this paper. The experimental results have revealed that our run-time environment utilize dual data memory banks efficiently and diminished usage of run-time memory




Jobs related to Memory architecture

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